SSM3515CCBZ-R7 datasheet(3/41 Pages) AD

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Data Sheet

SSM3515

Rev. A| Page 3 of 41

SPECIFICATIONS

PVDD = 12 V, VREG50/AVDD = 5 V (internal), VREG18/DVDD = 1.8 V (external), RL = 8 Ω + 33 μH, BCLK = 3.072 MHz and FSYNC =

48 kHz, TA = −40°C to +85°C, unless otherwise noted. The measurements are with a 20 kHz AES17 low-pass filter. The other load

impedances used are 4 Ω + 15 μH and 3 Ω +10 μH. Measurements are with a 20 kHz AES17 low-pass filter, unless otherwise noted.

The sine wave output powers above 20 W in 4 Ω cannot be continuous and may invoke the thermal limit indicator based on the power

dissipation capability of the board.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

DEVICE CHARACTERISTICS

Output Power/Channel

POUT

f = 1 kHz

RL = 8 Ω

THD + N = 1%, PVDD = 17 V

THD + N = 1%, PVDD = 12 V

8.4

THD + N = 1%, PVDD = 7 V

2.8

THD + N = 1%, PVDD = 5 V

1.4

THD + N = 10%, PVDD = 17 V

19.7

THD + N = 10%, PVDD = 12 V

10.5

THD + N = 10%, PVDD = 7 V

3.5

THD + N = 10%, PVDD = 5 V

1.8

RL = 4 Ω

THD + N = 1%, PVDD = 17 V

31.3

THD + N = 1%, PVDD = 12 V

15.8

THD + N = 1%, PVDD = 7 V

5.4

THD + N = 1%, PVDD = 5 V

2.8

THD + N = 10%, PVDD = 17 V

39.3

THD + N = 10%, PVDD = 12 V

19.7

THD + N = 10%, PVDD = 7 V

6.7

THD + N = 10%, PVDD = 5 V

3.4

Efficiency

POUT = 9 W, RL = 8 Ω, PVDD = 12 V

93.3

POUT = 9 W, RL = 8 Ω, PVDD = 12 V (low EMI mode)

93.2

POUT = 30 W, RL = 4 Ω, PVDD = 17 V

POUT = 30 W, RL = 4 Ω, PVDD = 17 V (low EMI mode)

87.8

Total Harmonic

Distortion + Noise

THD + N

POUT = 5 W into RL = 8 Ω, f = 1 kHz, PVDD = 16 V

0.004

Load Resistance

Ω

Load Inductance

μH

Output FET On Resistance

RON

110

mΩ

Overcurrent Protection

Trip Point

IOC

5.8

A peak

Average Switching

Frequency

fSW

300

kHz

Differential Output DC

Offset Voltage

VOOS

Gain = 12.6 V

±1

±5.0

POWER SUPPLIES

Supply Voltage Range

PVDD

Guaranteed from PSRR test

4.5

VREG50/AVDD

Internal

4.5

5.0

5.5

VREG18/DVDD

Internal or external

1.62

1.80

1.98

AC Power Supply

Rejection Ratio

PSRRAC

VRIPPLE = 1 V rms at 1 kHz

GAIN CONTROL

Measured with 0 dBFS input at 1 kHz

Output Voltage Peak

Analog gain setting = 8.4 V/V with PVDD = 17 V

8.4

V peak

Analog gain setting = 12.6 V/V with PVDD = 17 V

12.6

V peak

Analog gain setting = 14.0 V/V with PVDD = 17 V

V peak

Analog gain setting = 15.0 V/V with PVDD = 17 V

V peak

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