SSM3515CCBZ-R7 datasheet(19/41 Pages) AD

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Data Sheet

SSM3515

Rev. A| Page 19 of 41

THEORY OF OPERATION

OVERVIEW

The SSM3515Class-D audio amplifier features a filterless

modulation scheme that greatlyreduces the external component

count, conserving board space and reducing system cost. The

SSM3515 does not require an output filter; it relies on the

inherent inductance of the speaker coil and the natural filtering

of the speaker and human ear to recover the audio component

of the square wave output.

Most Class-D amplifiers use some variation of pulse-width

modulation (PWM), but the SSM3515 uses Σ-Δ modulation to

determine the switching pattern of the output devices, resulting

in a number of importantbenefits.Σ-Δ modulators do notproduce

a sharp peak with many harmonics in the AM broadcast band, as

pulse-width modulators often do. Σ-Δ modulation reduces the

amplitude of spectral components at high frequencies, reducing

EMI emission that may otherwise be radiated by speakers and

long cable traces. Due to the inherent spread spectrum nature of

Σ-Δ modulation,the need for oscillator synchronization is elimi-

nated for designs incorporatingmultiple SSM3515amplifiers.

The SSM3515also integrates overcurrent and temperature

protection and a thermal warning with optional programmable

gain reduction.

POWER SUPPLIES

The power supply pins on the SSM3515 are PVDD, VREG50/

AVDD, and VREG18/DVDD.

PVDD, the battery supply, is used for the output stage and also

supplies power to the 5 V regulator. In addition, it can be used

to supply power to the 1.8 V regulator. This pin must be

decoupled to ground using a 100 nF capacitor in parallel with a

1 µF MLCC capacitor to ground as close as possible to the

respective pins. In addition, a bulk electrolytic capacitor maybe

required depending onthe output power to supplythe current at

low frequency output. Typically, 220µF and 25 V is

recommended. This must be sized according to the power

supply regulation in the system.

VREG50/AVDD (5 V) is the analog supply used for the input

stage, modulator, power stage driver, and other blocks. It uses

the VREG50/AVDD pin. It is generated internally by the

integrated 5 V linear regulator. This pin must be decoupled to

ground using the 100 nF and 10 µF capacitor.

VREG18/DVDD (1.8 V) is the supply for the digital circuitry. It

uses the VREG18/DVDD pin. It can be generated internally

using an integrated 1.8 V linear regulator. Alternatively, an

external 1.8 V supply can be used to save the power dissipation.

The VREG18/DVDD pin must be decoupled to ground using

100 nF and 10 µF MLCC capacitors close to the pin.

POWER-UP SEQUENCE

If the REG_EN pin is tied to PVDD, the power-up sequence is

performed internally. As the PVDD voltage ramps up, the

VREG18/DVDD voltage (generated internally) also ramps up.

The typical wait time before the I2C commands can be sent to

the device depends on the PVDD supply ramp-up time.

If the REG_EN pin is tied low, ensure that 1.8 V is supplied

externally and that PVDD is greater than 4.5 V before sending

I2C commands to enable the device.

POWER-DOWN OPERATION

The SSM3515offers several power down options via I2C.

power-down modes.

Set the SPWDN bit to 1 to fully power down the device. Only

the I2C, 1.8 V regulator is kept alive.

The SSM3515monitors both the BCLK and FSYNC pins for clock

presence when in 2-wire mode.When no BCLK or FSYNCsignals

are present, the device automatically powers down all internal

circuitry to its lowest power state. When a BCLK or FSYNC

signal returns, the device automatically powers up following

its usual power up sequence.

When enabled, the APWDN_EN bit (auto power down),

activates a low power state as soon as 2048 consecutive zero

input samples are received. Only the I2C and digital audio input

blocks are kept active.

REG_EN PIN SETUP AND CONTROL

The REG_EN (regulator enable) pin enables or disables the

internal 1.8 V regulator.

Table 10. Regulator Enable Pin Function

REG_EN

1.8 V Regulator

Comment

Ground

Disabled

External 1.8 V

PVDD

Enabled

Internal 1.8 V

The status of the REG_EN pin determines if the 1.8 V supply is

generated internally or if it must be provided externally. If the

REG_EN pin is tied to PVDD, the internal 1.8 V regulator is

enabled. If the REG_EN pin is tied to ground, a 1.8 V supply

must be supplied externally to the VREG18/DVDD pin for the

device to operate. For the device to respond to I2C commands,

the 1.8 V supply must be stable.

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