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SSM3515CCBZ-R7 数据表(PDF) 9 Page - Analog Devices

部件名 SSM3515CCBZ-R7
功能描述  Audio Amplifier
PDF  41 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM3515CCBZ-R7 数据表(HTML) 9 Page - Analog Devices

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Data Sheet
SSM3515
Rev. A| Page 9 of 41
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
3
4
A
B
C
D
VREG50/
AVDD
AGND
PGND
BST–
SDA
ADDR
OUT–
OUT–
SCL
REG_EN
PVDD
PVDD
VREG18/
DVDD
FSYNC
OUT+
OUT+
SDATA
BCLK
PGND
BST+
E
Figure 6. Pin Configuration (Top Side View)
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
A1
VREG50/AVDD
AOUT
5 V Regulator Output.
A2
AGND
PWR
Analog Ground. It is recommended to connect the AGND pin to a single ground plane on the board.
A3
PGND
PWR
Power Stage Ground. The PGND pin is shorted internally. It is recommended to connect PGND to a
single ground plane on the board.
A4
BST−
AIN
Bootstrap Capacitor for OUT−.
B1
SDA
DIO
I2C Serial Data.
B2
ADDR
DIN
I2C Address Selection.
B3
OUT−
AOUT
Power Stage Inverting Output.
B4
OUT−
AOUT
Power Stage Inverting Output.
C1
SCL
DIN
I2C Clock.
C2
REG_EN
AIN
Regulator Enable Tie to PVDD to Enable Regulators.
C3
PVDD
PWR
Power Stage Supply.
C4
PVDD
PWR
Power Stage Supply.
D1
VREG18/DVDD
PWR
1.8 V Regulator Output/DVDD Input.
D2
FSYNC
DIN
TDM Frame Sync Input.
D3
OUT+
AOUT
Power Stage Noninverting Output.
D4
OUT+
AOUT
Power Stage Noninverting Output.
E1
SDATA
DIO
Serial Data Input to DAC.
E2
BCLK
DIN
TDM Bit Clock Input.
E3
PGND
PWR
Power Stage Ground. The PGND pin is shorted internally. It is recommended to connect PGND to a
single ground plane on the board.
E4
BST+
AIN
Bootstrap Capacitor for OUT+.
1 AOUT is analog output; PWR is power supply or ground pin; AIN is analog input; DIO is digital input/output; DIN is digital input.



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