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SSM3515CCBZ-R7 数据表(PDF) 6 Page - Analog Devices |
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SSM3515CCBZ-R7 数据表(HTML) 6 Page - Analog Devices |
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6 / 41 page  SSM3515 Data Sheet Rev. A| Page 6 of 41 DIGITAL TIMING CHARACTERISTICS All timing specifications are given for the default setting (I2S mode) of the serial input port. Table 5. I2C Port Timing Limit Parameter Min Max Unit Description I2C PORT fSCL 400 kHz SCL frequency tSCLH 0.6 µs SCL high tSCLL 1.3 µs SCL low tSCS 0.6 µs Setup time; relevant for repeated start condition tSCH 0.6 µs Hold time; after this period, the first clock is generated tDS 100 ns Data setup time tSCR 300 ns SCL rise time tSCF 300 ns SCL fall time tR 300 ns SDA rise time, not shown in Figure 2 tF 300 ns SDA fall time, not shown in Figure 2 tBFT 0.6 µs Bus-free time (time between stop and start) tHOLD 140 ns SCL falling to SDA rising 0 ns SCL falling to SDA falling Table 6. Digital Input Timing Limit Parameter TMIN TMAX Unit Description SERIAL PORT tBIL 15 ns BCLK low pulse width tBIH 15 ns BCLK high pulse width tSIS 6 ns SDATA setup, time to BCLK rising tSIH 6 ns SDATA hold, time from BCLK rising tLIS 10 ns FSYNC setup time to BCLK rising tLIH 5 ns FSYNC hold time to BCLK rising tBP 40 ns Minimum BCLK period Digital Timing Diagrams tSCH tSCS tBFT tSCF tDS tSCLL tHOLD tSCR tSCLH tSCH STOP CONDITION START CONDITION SDA SCL Figure 2. I2C Port Timing |
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