SSM3515CCBZ-R7 datasheet(22/41 Pages) AD

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SSM3515

Data Sheet

Rev. A| Page 22 of 41

In read mode, the SSM3515outputs the highest subaddress register

contents until the master device issues a no acknowledge, indi-

cating the end of a read. A no acknowledge conditionis when the

SDA line is not pulled low on the ninth clock pulse on SCL. Ifthe

highest subaddress location is reached while in write mode, the

data for the invalid byte is notloaded into anysubaddress register,

a no acknowledge is issued by the SSM3515, and the device

returns to the idle condition.

I2C Read and Write Operations

Figure 62 shows the timing of a single-word write operation.

Every ninth clock, the SSM3515issues an acknowledge (ACK)

by pulling SDA low.

Figure 63 shows the timing ofa burst mode writesequence. This

figure shows an example in which the targetdestinationregisters

are two bytes. The SSM3515increments its subaddress register

every byte because therequested subaddress corresponds to a

The timing ofa single word read operationis shown in Figure 64.

Note that the first R/W bit is 0, indicating a write operation.

This is because the subaddress still must be written to set up the

internal address. After the SSM3515 acknowledges the receipt of

the subaddress, the master must issue a repeated startcommand

followed by the chip address byte with the R/W set to 1 (read).

This causes the SSM3515SDA to reverse and begin driving data

back to the master. The master then responds every ninth pulse

with an acknowledge pulse to the SSM3515. See Table 15 for a

list of abbreviations in Figure 62 through Figure 65.

Table 13. I2C Device Address Byte Format Using the ADDR Pin1

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

R/W

1 X means don’t care.

Table 14. ADDR Pin to I2C Device Address Mapping

ADDR Pin

ADDR Voltage

I2C Address Bit 5

I2C Address Bit 6

GND

Not applicable

Pull-Down 47 kΩ Resistor

0.25 × VREG18/DVDD

Open

0.5 × VREG18/DVDD

Pull-Up 47 kΩ Resistor

0.75 × VREG18/DVDD

DVDD

Table 15. Abbreviations for Figure 62 Through Figure 65

Symbol

Meaning

Start bit

Stop bit

Acknowledge by master

Acknowledge by slave

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