SSM3515CCBZ-R7 datasheet(33/41 Pages) AD

33 / 41 page

Data Sheet

SSM3515

Rev. A| Page 33 of 41

SAI CONTROL 1 REGISTER

Address: 0x04, Reset: 0x11, Name: SAI Control 1

Table 25. Bit Descriptions for SAI Control 1

Bits

Bit Name

Settings

Description

Reset

Access

DAC_POL

DAC Output Polarity.

0x0

R/W

Normal Operation.

Invert the Audio Output Signal.

BCLK_POL

BCLK Polarity Control.

0x0

R/W

Rising Edge of BCLK is Used to Register SDATA.

Falling Edge of BCLK is Used to Register SDATA.

[5:3]

TDM_BCLKS

Number of BCLKs per Chip in TDM Mode. Any number of BCLK cycles per FSYNC

can be used in stereo modes (I2S/LJ) or in TDM mode with only one chip. When in

TDM mode and having multiple chips on the TDM bus, the number of BCLKs per

chip must be defined.

0x2

R/W

000

16 BCLKs per Chip in TDM.

001

24 BCLKs per Chip in TDM.

010

32 BCLKs per Chip in TDM.

011

48 BCLKs per Chip in TDM.

100

64 BCLKs per Chip in TDM.

FSYNC_MODE

FSYNC Mode Control.

0x0

R/W

Low FSYNC is Left Channel in Stereo Modes or Pulsed FSYNC Mode in TDM

Modes.

High FSYNC is Left Channel in Stereo Modes or 50% FSYNC Mode in TDM Modes.

SDATA_FMT

Serial Data Format.

0x0

R/W

I2S/Delay by One from FSYNC Edge.

Left Justified/No Delay from FSYNC Edge.

SAI_MODE

Serial Interface Mode Selection.

0x1

R/W

Stereo Modes (I2S, LJ).

TDM/PCM Modes.

[7] DAC_POL (R/W)

DAC Output Polarity

0: Normal Operation.

1: Invert the Audio Output Signal.

[0] SAI_MODE (R/W)

Serial Interface Mode Selection

0: Stereo Modes (I2S,LJ)

1: TDM/PCM Modes.

[6] BCLK_POL (R/W)

BCLK PolarityControl

0: Rising Edge of BCLK is used to register

SDATA.

1: Falling Edge of BCLK is used to register

SDATA.

[1] SDATA_FMT (R/W)

Serial Data Format

0: I2S/Delay by one from FSYNC edge.

1: Left Justified/No delayfrom FSYNC edge.

[2] FSYNC_MODE (R/W)

FSYNC Mode Control

0: Low FSYNC is Left Channel in Stereo

Modes or Pulsed FSYNC Mode in TDM Modes.

1: High FSYNC is Left Channel in Stereo

Modes or 50% FSYNC Mode in TDM Modes.

[5:3] TDM_BCLKS (R/W)

Number of BCLKs per chip in TDM mode

000: 16 BCLKs per chip in TDM.

001: 24 BCLKs per chip in TDM.

010: 32 BCLKs per chip in TDM.

011: 48 BCLKs per chip in TDM.

100: 64 BCLKs per chip in TDM.

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