MAS6503 datasheet(15/34 Pages) MAS

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DA6503.005

14 December 2016

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MEASUREMENT CONTROL REGISTER 1 (E2/62HEX)

Measurement control register 1 (E2/62HEX) is for

configuring the first half of the measurement

settings. The second half of measurement settings

is configured by Measurement control register 2

(E3/63HEX) which is also used for starting a

conversion.

DIV bit selects between normal clock (DIV=0) and

divided by 4 clock (DIV=1). By default DIV=0

selection is used. Note also that the MCLK clock

frequency can be further divided by 2 using the

Test register (E1/61HEX) ENDIV bit. See Electrical

Characteristics page 5 for MCLK options as

function of DIV and ENDIV bits.

ISCR bits select full scale input signal range from

four options. The table 3 input signal range voltage

values correspond to values at supply voltage

VDD=2.7V. At other supply voltage the ISCR values

scale directly with VDD due to ratiometric A/D

converter principle. The linear input signal range is

80% (10%...90%) of the full scale input range. See

also Input Signal Range Definitions in the

Application Information section.

ENOFS bit is for enabling offset voltage to the input

signal conversion range (ENOFS=0 disabled,

ENOFS=1 enabled).

SGNOFS bit is for selecting sign of the input signal

conversion range offset (SGNOFS=0 positive,

SGNOFS=1 negative).

OFS bits select input signal conversion range offset

from four options.

ENREG is for enabling internal voltage regulator

(ENREG=0 disabled, ENREG=1 enabled). When

enabled the regulator

is turned on during

conversions and automatically turned off after each

conversion to save power. However note that if in

the Test register FOSC=1 and if ENREG=1 the

regulator is forced on all the time even when

measurement is not running. In the VDD level

monitoring mode it is necessary to disable the

internal regulator (ENREG=0).

See also Regulator output voltage control register

(EB/6BHEX) for internal voltage regulator output

voltage selections.

Table 3. Measurement control register 1 (E2/62HEX) description

Bit

Number

Bit Name

Description

Value

Function

DIV

Clock Divider by 4

Normal clock

Divided by 4 clock

6-5

ISCR

Input Signal Conversion

Range (full scale)

373mV

253mV

172mV

115mV

at VDD=2.7V

ENOFS

Offset Enable

Offset disabled

Offset enabled

SGNOFS

Offset Sign

Positive offset

Negative offset

2-1

OFS

Offset value

40mV

57mV

86mV

126mV

at VDD=2.7V

ENREG

Regulator Enable

Voltage regulator disabled

Voltage regulator enabled

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