DA6503.005

14 December 2016

29 (34)

APPLICATION INFORMATION

VDD rise time > 1ms

If the VDD rise time can exeed 1ms it is necessary to keep the MAS6503 in reset during power up using the

XCLR reset pin. Violating this may risk EEPROM memory integrity. Figures 12 a-c present examples of external

POR circuits providing reset via the XCLR pin in case the VDD rise time can exceed 1ms.

Figures 12 a, b, c. External XCLR reset circuit examples for VDD rise time >1ms

The XCLR pin has internal pull up with 8µA current which makes the pull up resistor unnecessary. In the figure

12c the external POR circuit delay can be calculated as follows.

VDD

A

C

t

POR







8

The POR delay should be made larger than the maximum VDD rise time. For example if the longest possible

VDD rise time is 50ms and VDD=2.7V then we could choose capacitor value which gives at least 100ms POR

Resolution Improvement – Averaging

An averaging technique can be used to remove

conversion errors caused by noise and thus

improve measurement resolution. By doing several

A/D conversions and calculating the average result

it’s possible to average out noise. Theoretically the

noise is reduced by a factor

N

where N is the

number of averaged samples. A/D converter

nonlinearities cannot be removed by averaging.