DA6503.005

14 December 2016

22 (34)

2-WIRE SERIAL DATA INTERFACE (I2C BUS)

Figure 4. I2C bus protocol definitions

Bus communication includes Acknowledge (A) and

not Acknowledge (N) messages. To send an

acknowledge the receiver device pulls the SDA low

for one SCL clock cycle. For not acknowledge (N)

the receiver device leaves the SDA high for one

SCL clock cycle in which case the master can then

generate either a Stop (P) bit to abort the transfer,

or a repeated Start (Sr) bit to start a new transfer.

Abbreviations:

A= Acknowledge by Receiver

N = Not Acknowledge by Receiver

S = Start

Sr = Repeated Start

P = Stop

= from Master (MCU) to Slave (MAS6503)

= from Slave (MAS6503) to Master (MCU)

Conversion Starting – Write Sequence

Conversion is started by writing configuration bits

into the Measurement control registers 1 and 2

is illustrated in Table 10.

Table 10. MAS6503 I2C bus write sequence of two consecutive Measurement control registers 1 and 2

S

AW

A

MC1

A

DC1

A

DC2

A

P

Abbreviations:

Ax = Conversion Result Registers’ Addresses; MSB

DC1 = Measurement Control Register 1 Data

DC2 = Measurement Control Register 2 Data

Dx = Conversion Result Register Data; MSB (x=M),

ISB (x=I) or LSB (x=L)

Each serial bus operation, like write, starts with the

start (S) bit (see figure 4). After start (S) the

MAS6503 device address with write bit (AW, see

table 9) is sent followed by an Acknowledge (A).

After this the Measurement control register 1

address (see table 1) is sent and followed by an

Acknowledge (A). Next the Measurement control

register 1 data (DC1, see table 3) is written and

followed by an Acknowledge (A). Due to register

address auto increment to the next register address

the Measurement control register 2 data (DC2, see

table 4) can follow right after first data byte. After

acknowledge of second data byte the serial bus

operation is ended with stop (P) command (see

figure 4). A new A/D conversion starts right after

Measurement control register 2 bits are received.

A/D Conversion

After power on reset or external reset (XCLR) the

EOC output is high. After an A/D conversion is

started the EOC output is set low until the

conversion is finished and the EOC goes back high,

indicating that the conversion is done and data is

ready for reading. The EOC is set low only by

starting a new conversion. To save power the

internal oscillator runs only during conversion.

During an A/D conversion the input signal is

sampled

continuously

leading

to

an

output

conversion result that is a weighted average of the

samples taken.