NUC505-YO2G datasheet(6/130 Pages) NUVOTON

6 / 130 page

NUC505

July. 26, 2018

Page 6 of 130

Rev.1.08

List of Figures

Figure 4.1-1 NuMicro

® NUC505 Base Series Selection Code....................................................... 16

Figure 4.2-1 NuMicro

® NUC505DLA LQFP 48-pin Diagram.......................................................... 17

Figure 4.2-2 NuMicro

® NUC505DL13Y LQFP 48-pin Diagram...................................................... 18

Figure 4.2-3 NuMicro

® NUC505YLA QFN 48-pin Diagram............................................................ 19

Figure 4.2-4 NuMicro

® NUC505YLA2Y QFN 48-pin Diagram ....................................................... 20

Figure 4.2-5 NuMicro

® NUC505DSA LQFP 64-pin Diagram ......................................................... 21

Figure 4.2-6 NuMicro

® NUC505DS13Y LQFP 64-pin Diagram ..................................................... 22

Figure 4.2-7 NuMicro

® NUC505YO13Y QFN 88-pin Diagram....................................................... 23

Figure 5.1-1 NuMicro

® NUC505 Block Diagram ............................................................................ 68

Figure 6.1-1 Cortex

® -M4 Block Diagram........................................................................................ 69

Figure 6.2-1 NuMicro

® NUC505 Power Distribution Diagram........................................................ 74

Figure 6.2-2 SRAM Block Diagram ................................................................................................ 76

Figure 6.2-3 SRAM Memory Organization ..................................................................................... 77

Figure 6.2-4 Vector Map Module Block.......................................................................................... 78

Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 85

Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 86

Figure 6.3-3 Crystal Oscillator Circuit ............................................................................................ 87

Figure 6.4-1 I/O Pin Block Diagram ............................................................................................... 88

Figure 6.11-1 I

2C Bus Timing......................................................................................................... 95

Figure 7.3-1 Typical Crystal Application Circuit ........................................................................... 109

Figure 7.4-1 Power-up Ramp Condition ...................................................................................... 115

Figure 7.4-2 I

2C Timing Diagram ................................................................................................. 118

Figure 7.4-3 SPI Master Mode Timing Diagram .......................................................................... 119

Figure 7.4-4 SPI Slave Mode Timing Diagram ............................................................................ 120

Figure 7.4-5 I2S Master Mode Timing Diagram ........................................................................... 122

Figure 7.4-6 I

2S Slave Mode Timing Diagram.............................................................................. 122

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