NUC505-YO2G datasheet(88/130 Pages) NUVOTON

88 / 130 page

NUC505

July. 26, 2018

Page 88 of 130

Rev.1.08

General Purpose I/O (GPIO)

6.4

6.4.1

Overview

The NUC505 series has up to 52 General Purpose I/O pins to be shared with other function pins

depending on the chip configuration. The 52 pins are arranged in 4 ports named as PA, PB, PC,

and PD. PA and PB have 16 pins on port, PC has 15 pins on port, and PD has 5 pins on port.

Each of the 52 pins is independent and has the corresponding register bits to control the pin

mode function and data.

The I/O type of each I/O pins can be configured by software individually as Input or Push-pull

output mode. After the chip is reset, the I/O mode of all pins is input mode with no pull-up and

pull-down enable (except PB.2, it is pull-up enable). Each I/O pin has an individual pull-up and

pull-down resistor which is about 40 k

 ~ 50 k for VDD and Vss. User can set Px_PUEN to

control I/O pins to pull-up or pull-down.

PAD

PIN[n]

(Px_PIN)

PULLSEL[0]

(Px_PUEN)

PULLSEL[1]

(Px_PUEN)

MODE[n]

(Px_MODE)

DOUT[n]

(Px_DOUT)

Note: Px_ means PA_, PB_, PC_, or PD_

Figure 6.4-1 I/O Pin Block Diagram

6.4.2

Features



Two I/O modes:



Push-Pull Output mode



Input only with high impendence mode



CMOS/Schmitt trigger input selectable (refers SYS_GPAIBE register on TRM)



I/O pin can be configured as interrupt source with edge setting

NUC505-YO2G 数据表(PDF) 88 Page - Nuvoton Technology Corporation

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