NUC505-YO2G datasheet(83/130 Pages) NUVOTON

83 / 130 page

NUC505

July. 26, 2018

Page 83 of 130

Rev.1.08

TM3_INT

Timer3 interrupt

SDH_INT

SDH interrupt

PWM0_INT

PWM0 interrupt

PWM1_INT

PWM1 interrupt

PWM2_INT

PWM2 interrupt

PWM3_INT

PWM3 interrupt

RTC_INT

Real Time Clock interrupt

SPI0_INT

SPI0 interrupt

I2C1_INT

I2C1 interrupt

I2C0_INT

I2C0 interrupt

UART0_INT

UART0 interrupt

UART1_INT

UART1 interrupt

ADC_INT

ADC interrupt

wwdt_INT

Window Watch Dog Timer interrupt

USBH_INT

USB Host 1.1 interrupt

UART2_INT

UART2 interrupt

LVD_INT

Low Voltage Detection interrupt

SPI1_INT

SPI1 interrupt

Reserved

Table 6.2-5 Interrupt Number Table

Operation Description

6.2.9.2

NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or

Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear

policy, both registers reading back the current enabled state of the corresponding interrupts. When an

interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the

interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until

cleared by reset or an exception return. Clearing the enable bit prevents new activations of the

associated interrupt.

NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to

enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register

respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading

back the current pended state of the corresponding interrupts. The Clear-Pending Register has no

effect on the execution status of an Active interrupt.

NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register

supporting four interrupts, and each interrupt uses MSB 4 bits of the 8-bit field).

The general registers associated with the NVIC are all accessible from a block of memory in the

System Control Space and will be described in next section.

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