NUC505-YO2G datasheet(70/130 Pages) NUVOTON

70 / 130 page

NUC505

July. 26, 2018

Page 70 of 130

Rev.1.08

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Banked Stack Pointer (SP).

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Hardware integer divide instructions, SDIV and UDIV.

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Handler and Thread modes.

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Thumb and Debug states.

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Support for interruptible-continued instructions LDM, STM, PUSH, and POP for

low interrupt latency.

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Automatic processor state saving and restoration for low latency Interrupt Service

Routine (ISR) entry and exit.

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Support for ARMv6 big-endian byte-invariant or little-endian accesses.

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Support for ARMv6 unaligned accesses.

 Floating Point Unit (FPU) in the Cortex

® -M4F processor providing:

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32-bit instructions for single-precision (C float) data-processing operations.

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Combined Multiply and Accumulate instructions for increased precision (Fused

MAC).

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Hardware support for conversion, addition, subtraction, multiplication with optional

accumulate, division, and square-root.

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Hardware support for denormals and all IEEE rounding modes.

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32 dedicated 32-bit single precision registers, also addressable as 16 double-word

registers.

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Decoupled three-stage pipeline.

 Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to

achieve low latency interrupt processing. Features include:

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External interrupts. Configurable from 1 to 240; the NUC505 has been configured

with 32 interrupts.

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Bits of priority, configurable from bit 3 to bit 7.

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Dynamic reprioritization of interrupts.

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Supports priority grouping which enables selection of preempting interrupt levels

and non-preempting interrupt levels.

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Supports tril-chaining and late arrival of interrupts, which enables back-to- back

interrupt processing without the overhead of state saving and restoration between

interrupts.

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Processor state automatically saved on interrupt entry, and restored on interrupt

exit with on instruction overhead.

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Supports Wake-up Interrupt Controller (WIC) with Power-down mode.

 Memory Protection Unit (MPU). An optional MPU for memory protection, including:

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Eight memory regions.

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Sub Region Disable (SRD), enabling efficient use of memory regions.

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The ability to enable a background region that implements the default memory

map attributes.

 Low-cost debug solution that features:

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