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NUC505-YO2G 数据表(PDF) 85 Page - Nuvoton Technology Corporation |
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NUC505-YO2G 数据表(HTML) 85 Page - Nuvoton Technology Corporation |
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85 / 130 page ![]() NUC505 July. 26, 2018 Page 85 of 130 Rev.1.08 6.3.2 Clock Diagram 12 MHz PLL_FOUT SRAM01 RTC CPU SRAM23 External 32.768 kHz CPUCLK HCLK 12 MHz SPIM APLL_FOUT 12 MHz Internal 32.768 kHz 1 0 External 32.768 kHz PLL_FOUT 1 0 12 MHz 1/(SYSCLK_N+1) PCLK 1/(PCLKDIV_N+1) Internal 32.768 kHz I2C0 I2C1 RTC_CLKSRC[0] RTC_32K RTC_32K 1 0 12MHz CLKDIV4[24] CLKDIV0[7] RTC_32K 1 0 12MHz CLKDIV4[25] TMR1 RTC_32K 1 0 12MHz CLKDIV4[26] TMR2 RTC_32K 1 0 12MHz CLKDIV5[24] TMR 3 RTC_32K 1 0 12MHz CLKDIV5[25] WDT PLL_FOUT 1 0 12MHz CLKDIV5[26] PWM PLL_FOUT 1 0 12MHz CLKDIV3[20] UART2 PLL_FOUT 1 0 12MHz CLKDIV3[12] UART1 PLL_FOUT 1 0 12MHz CLKDIV3[4] UART0 Reserved 12MHz APLL_FOUT PLL_FOUT CLKDIV2[25:24] 11 10 01 00 I 2S 1/(TMR2DIV+1) 1/(TMR1DIV+1) TMR0 1/(TMR0DIV+1) 1/(PWMDIV+1) 1/(WDGCLK_N+1) 1/(TMR3DIV+1) 1/(UART2DIV+1) 1/(UART1DIV+1) 1/(UART0DIV+1) 1/(I2SDIV+1) PLL_FOUT 1 0 12MHz CLKDIV2[29] SPI1 1/(SPI1_CLKDIV+1) PLL_FOUT 1 0 12MHz CLKDIV2[28] SPI0 1/(SPI0_CLKDIV+1) PLL_FOUT 1 0 12MHz CLKDIV1[28] ADC 1/(ADCDIV+1) 1 0 SysTick CLKDIV1[30] CPUCLK 1/(STICKDIV+1) 12MHz PLL_FOUT 1 0 12MHz SDHC 1/(SDHDIV+1) SYST_CSR[2] PLL_FOUT 1 0 12MHz USBD 1/(USBDDIV+1) PLL_FOUT USBH 1/(USBHDIV+1) CLKDIV0[23] Figure 6.3-1 Clock Generator Global View Diagram |
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