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NUC505-YO2G 数据表(PDF) 79 Page - Nuvoton Technology Corporation

部件名 NUC505-YO2G
功能描述  ARM짰 Cortex짰-M4 32-bit Microcontroller
PDF  130 Pages
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制造商  NUVOTON [Nuvoton Technology Corporation]
网页  http://www.nuvoton.com
标志 NUVOTON - Nuvoton Technology Corporation

NUC505-YO2G 数据表(HTML) 79 Page - Nuvoton Technology Corporation

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NUC505
July. 26, 2018
Page 79 of 130
Rev.1.08
6
USBH
6
SDH
8 (Highest)
I
2S
Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode If two or more master modules request to
access AHB bus at the same time, the higher priority request will get the permission to access AHB
bus.
Priority Sequence
(PRISEL = 0)
AHB Bus Priority
1 (Lowest)
Cortex-M4 I
2
Cortex-M4 D
3
Cortex-M4 System
4
SPIM
5
USBD
6
USBH
6
SDH
8 (Highest)
I
2S
Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode
The SPI flash controller normally has the lowest priority (except CPU interface) under the fixed priority
mode. The NUC505 provides a mechanism to raise the priority of CPU request to the highest. If the
CPUHPRI bit (bit-4 of SYS_AHBCTL control register) is set to 1, the PRISTS bit (bit-5 of
SYS_AHBCTL control register) will be automatically set to 1 while an unmasked external IRQ occurs.
Under this circumstance, the ARM core will become the highest priority to access AHB bus.
The programmer can recover
the original priority order by directly writing “1” to clear the PRISTS bit.
For example, this can be done that at the end of an interrupt service routine. Note that PRISTS only
can be automatically set to 1 by an external interrupt when CPUHPRI = 1. It will not take effect for a
programmer to directly write 1 to PRISTS
to raise ARM core’s AHB priority.
Round Robin Priority Mode
6.2.7.2
Round-robin priority mode is selected if PRISEL = 1. The AHB bus arbiter uses a round robin
arbitration scheme for every master module to gain the bus ownership in turn. That is the requestor
having the highest priority becomes the lowest-priority requestor after it has been granted access.
Rotate rule Example
6.2.7.3
In the default sequence of AHB Master Bus, the priority is I
2S>SDH > USBH > USBD >SPIM >M4(S) >
M4(D) > M4(I).



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