GS3471 datasheet(30/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

30 of 179

Semtech

www.semtech.com

4.4.4 DVB-ASI Mode

When in DVB-ASI mode (SMPTE_BYPASS = LOW and DVB_ASI = HIGH), the retimer PLL

locks to a DVB-ASI stream. In DVB-ASI mode, the parallel outputs are configured

appropriately as described in 4.11.3 Parallel Output in DVB-ASI Mode. None of the

SMPTE detection and processing functions are available in this mode.

4.5 Digital Differential Input (DDI/DDI)

The GS3471 can accept two serial digital inputs compliant with SMPTE ST 424, SMPTE

292, and SMPTE ST 259-C– however, only one of the input serial data streams can be

retimed. The GS3471 contains a 100Ω differential input buffer which can be DC-coupled

to Semtech equalizers, but only if equalizer output stage is connected to 1.2V.

Otherwise must be AC coupled.

See Figure 4-1for a visualization of the Flex Input Loopback.

INPUT_CONFIG[3:2] allows for selection of DDI or SDI into the parallel retimed output

and DDO path.

LOS_CTRL[8] register contains the LOS_AFE_SEL bit, which allows for selection of DDI

or SDI for LOS sensing.

4.6 Serial Digital Input (SDI/SDI)

The GS3471 can accept serial digital inputs compliant with SMPTE ST 424, SMPTE 292,

and SMPTE ST 259-C.

Please see the Typical Application Circuit for how to terminate this input.

4.6.1 Upstream Launch Swing Compensation

The GS3471 has automatic gain control that is based on the assumption that the cable

driver in the upstream device is SMPTE compliant and has a launch swing of



800mVppd ±10%.

When the source amplitude is known to be non-SMPTE compliant, a compensation

adjustment can be made. The GS3471 can adjust for nominal launch swings between

250mVppd to 1000mVppd, in approximately 50mVppd increments. Upstream launch

swing compensation can be adjusted using the LAUNCH_SWING_COMPENSATION

bits in EQ_CONF_REG_2 register. The default value is 800mVppd (1011b).

4.7 Serial Digital Loop-Through Output

The GS3471 contains a differential serial digital output buffer. This output provides an

active loop-through of the input signal. It can be a reclocked or non-reclocked version

of the input used for processing or a non-reclocked version of the other input. Moreover,

selection of the loop-through output is independent of the selection of the signal going

into the de-serializer block.

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