GS3471 datasheet(83/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

83 of 179

Semtech

www.semtech.com

4.21.3 Audio Processing

4.21.3.1 Audio Clock Generation

For SD and HD/3G audio, a single set of audio frequencies is generated for all audio

channels.

For Mapping structure one signals (1080p 50, 59.94, or 60 or 2048p 50, 59.94, or 60), the

pixel clock is 148.5(/M)MHz, and the phase data are based on this rate. An Audio Master

Clock (AMCLK) is also generated. The frequency is selectable via the host interface as:

•

fs x 128

•

fs x 256

•

fs x 512

In SD mode, audio clocks are derived from the PCLK.

In HD/3G modes, audio clocks are derived from the two embedded audio clock phase

words in the audio data packet.

The audio de-embedder also includes a Flywheel block to overcome any inconsistencies

in the embedded audio clock phase information.

If the audio phase data is not present or incorrect, the

INVALID_EMBEDDED_PHASE[B:A] bit in the host interface will be asserted and audio

will be de-embedded using a clock derived from PCLK and the M value.

Alternatively, when the IGNORE_PHASE bit in the host interface is set HIGH, the M value

can be programmed via the host interface. This can be done by setting the FORCE_M

bit HIGH, and programming the desired value into FORCE_MEQ1001. The correct value

can be obtained by reading the M bit from the Video Core Registers.

If the ADPLL is locked to phase data and audio data packets are lost or corrupted, the

Clock Generator will flywheel for up to four audio data packets.

If the IGNORE_PHASE bit in the host interface is HIGH, the clock will free-run based on

the video format, the PCLK and the M value, independent of the

INVALID_EMBEDDED_PHASE[B:A] bit.

In the 720p/24 video format, the total line length is 4125 pixels, which requires a

resolution of 13 bits for the audio clock phase words in the embedded audio data

packets. SMPTE ST 299 only specifies a maximum of 12 bits resolution. The revised

versions of SMPTE ST 299 require using bit 5 of UDW1 in the audio data packet as the

MSB (ck13) for the audio clock phase data, providing 13 bits resolution.

Some audio encoders may hold the clock phase value at a maximum value when

reached, until reset at the end of the line. This produces a small amount of audio phase

jitter for the period of one sample.

To overcome this issue, the audio de-embedder checks for all cases. On detection of the

maximum value, a comparison is made between previous clock phases and the correct

position interpolated. If the clock phase data value starts to decrease, the de-embedder

checks to see if bit 5 (ck13) of UDW1 in the audio data packet is asserted. If ck13 is

asserted, the correct value is used. If ck13 is not set, the correct position is interpolated.

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