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GS3471 数据表(PDF) 2 Page - Semtech Corporation |
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GS3471 数据表(HTML) 2 Page - Semtech Corporation |
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2 / 179 page ![]() GS3471 Final Data Sheet Rev.4 PDS-060498 September 2017 2 of 179 Semtech www.semtech.com Description The GS3471 is a multi-rate SDI Receiver which includes complete SMPTE processing. The SMPTE processing features can be bypassed to support signals with other coding schemes. Multi-link UHD can be supported when multiple GS3471devices are used. The GS3471 integrates Semtech's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. The device features a dual input buffer with a 2x2 MUX. The 2x2 MUX can select between either input for de-serialization and can route either of the two inputs to the serial loopback independently (reclocked or non-reclocked). In addition, the integrated Retimer with an internal VCO provides a wide Input Jitter Tolerance (IJT). Configurable Power-down modes are available and allows for increased flexibility. Each Power-down mode enables power savings to a varying degree by selectively enabling or disabling key features. Some of the options available in Power-down mode are CSR access, PCLK, retimed DDO loop-through output, and non-retimed DDO loop-through output. Enabling or disabling each of these options will offer power consumption levels to suit the application's requirements. The device has three other basic modes of operation which include: • SMPTE mode • DVB-ASI mode • Data-Through mode The GS3471 includes an audio de-embedder and audio clocks are internally generated. Up to eight channels (two audio groups) of serial digital audio may be extracted from the video data stream, in accordance with SMPTE ST 272-C and SMPTE ST 299. GS3471 Functional Block Diagram DDI Retimer Buffer DDO De-Scramble Sync Detect CRC Check CRC Insertion Parallel Output Audio Extraction ANC Extraction FIFO RC Bypass DDO DDO Input Switch DDI DDI CT0 IO_VDD DOUT[19:0] PCLK STAT[5:0] AOUT_1_2 AOUT_3_4 AOUT_5_6 AOUT_7_8 AUDIO_EN/DIS ACLK WCLK AMCLK SDI SDI Host Interface JTAG Test Frequency Reference POR PWR_DWN EQ AGC AGC CT1 |
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