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GS3471 数据表(PDF) 23 Page - Semtech Corporation |
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GS3471 数据表(HTML) 23 Page - Semtech Corporation |
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23 / 179 page  GS3471 Final Data Sheet Rev.4 PDS-060498 September 2017 23 of 179 Semtech www.semtech.com 4.2 Device Power-Up The GS3471 is designed to operate in a multi-voltage environment which allows any power-up sequence to be used. Supply pins can all be powered up in any order. 4.2.1 Power-Down Mode The PWR_DWN pin reduces power to a minimum by disabling various device features. When the PWR_DWN pin is de-asserted, the device returns to its previous operating condition within 1 second, without requiring input from the host interface. There are several power-down options which can be configured through GSPI prior to the device going into power-down. Table 4-1 provides a summary of the supported power-down options by accessing the POWER_DOWN register. When the equalized input is not in use, it can be powered down using SLEEP. Additionally, the equalized input can be placed in an automatic sleep mode, whereby it is automatically powered down when no carrier is present and automatically powered up when carrier is present. This mode is selected using SLEEP. Table 4-1: Power-down Mode Power-down Mode CSR Access DDO Loop-through Mode PCLK Mode Power-down PD_PCLK_ENABLE = 0 SERIAL_LOOPBACK_EN = 0 PD_CSR_ACCESS = 0 RC_BYP = X No DDO Disabled PCLK Disabled Power-down with CSR Access PD_PCLK_ENABLE = 0 SERIAL_LOOPBACK_EN = 0 PD_CSR_ACCESS = 1 RC_BYP = X Yes DDO Disabled PCLK Disabled Power-down with PCLK PD_PCLK_ENABLE = 1 SERIAL_LOOPBACK_EN = 0 PD_CSR_ACCESS = X RC_BYP = X Yes DDO Disabled PCLK Enabled Power-down with DDO PD_PCLK_ENABLE = 0 SERIAL_LOOPBACK_EN = 1 PD_CSR_ACCESS = X RC_BYP = 1 No DDO Enabled Non-retimed PCLK Disabled |
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