GS3471 datasheet(60/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

60 of 179

Semtech

www.semtech.com

4.18 Video Signal Error Detection & Indication

The GS3471 includes a number of video signal error detection functions. These are

provided when operating in SMPTE mode (SMPTE_BYPASS = HIGH).

Signal errors that can be detected include:

1. TRS errors

2. HD line based CRC errors

3. EDH errors

4. HD line number errors

5. Device lock error

6. Ancillary data checksum errorsl

The GS3471 has two different registers for each set of error flags, ERROR_STAT_[2:1]

and ERROR_STAT_[2:1]_STICKY. ERROR_STAT_[2:1] registers are cleared on write,

when not locked, on a change of video standard, and once per frame.

ERROR_STAT_[2:1]_STICKY registers are read only and only cleared on read and reset.

ERROR_MASK_[3:1] are also provided, allowing the user to select which error

conditions are reported. Each bit of the ERROR_MASK register corresponds to a unique

error type. Please refer to Table 4-13 for a description of the ERROR_MASK register bits.

Separate interrupt enable (INT_ENABLE) registers for SD and HD audio cores are also

provided, allowing select error conditions to be reported. Each bit of each

ERROR_MASK register corresponds to a unique error type.

By default (at power-up or after system reset), all bits of the ERROR_MASK registers are

zero, enabling all errors to be reported. Individual error detection may be disabled by

setting the corresponding bit HIGH in the mask registers.

Error conditions are indicated by a VIDEO_ERROR signal and an AUDIO_ERROR signal,

which are available for output on the multifunction I/O output pins. The two signals are

also combined into a summary DATA_ERROR signal, which is also available on the

multifunction I/O pins. These signals are normally HIGH, but are set LOW by the device

when an error condition has been detected.

These signals are a logical 'NOR' of the appropriate error status flags stored in the

ERROR_STAT_[2:1] register, which are gated by the bit settings in the

ERROR_MASK_[3:1] registers. When an error status bit is HIGH and the corresponding

error mask bit is LOW, the corresponding DATA_ERROR signal is set LOW by the device.

All bits of the error status register, including the LOCK_ERR bit, is set LOW during

system reset.

Table 4-13 shows the ERROR_STAT_[2:1] register.

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