GS3471 datasheet(79/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

79 of 179

Semtech

www.semtech.com

Figure 4-45: Serial Audio, Right Justified, MSB First

4.21.2.1 AES/EBU Mode

In AES/EBU output mode, the audio de-embedder uses a 128fs (6.144MHz audio bit

clock) clock as shown in Figure 4-46.

Figure 4-46: AES/EBU Audio Output to Bit Clock Timing

The timing of the serial audio output signals and the ACLK output signal is shown in

Figure 4-47: ACLK to Data Signal Output Timing.

Figure 4-47: ACLK to Data Signal Output Timing

4.21.2.2 Audio Data Packet Extraction Block

The audio de-embedder looks for audio data packets on every line of the incoming

video.

The audio data must be embedded according to SMPTE ST 272 (SD) or



SMPTE ST 299/299-1/299-2 (HD or 3G).

In 3G Level A signals, the audio data packets must be embedded only in Data Stream 2.

In 3G Level B signals, the audio data packets must be embedded in the Data Stream 2 of

either Link A or Link B and have a data rate of 74.25MHz.

WCLK

ACLK

AOUT_[8_7:2_1]

MSB

LSB

MSB

LSB

Channel A (Left)

Channel B (Right)

AMCLK

(128fs)

AOUT_1_2, AOUT_3_4

AOUT_5_6, AOUT_7_8

6.144MHz

AOUT

ACLK

128fs = 162.76ns (AES/EBU)

64fs = 325.52ns (other modes)

20%

80%

20%

80%

toh

tod

WCLK

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