数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

GS3471 数据表(PDF) 28 Page - Semtech Corporation

部件名 GS3471
功能描述  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  SEMTECH [Semtech Corporation]
网页  http://www.semtech.com
标志 SEMTECH - Semtech Corporation

GS3471 数据表(HTML) 28 Page - Semtech Corporation

Back Button GS3471 Datasheet HTML 24Page - Semtech Corporation GS3471 Datasheet HTML 25Page - Semtech Corporation GS3471 Datasheet HTML 26Page - Semtech Corporation GS3471 Datasheet HTML 27Page - Semtech Corporation GS3471 Datasheet HTML 28Page - Semtech Corporation GS3471 Datasheet HTML 29Page - Semtech Corporation GS3471 Datasheet HTML 30Page - Semtech Corporation GS3471 Datasheet HTML 31Page - Semtech Corporation GS3471 Datasheet HTML 32Page - Semtech Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 28 / 179 page
background image
GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
28 of 179
Semtech
www.semtech.com
Figure 4-5: EQ_STAT Output MUXing
4.4 Modes of Operation
4.4.1 Auto and Manual Mode
The lock detection algorithm is a continuous process, beginning at device power-up or
after a system reset. It continues until the device is powered down or held in reset.
The device first determines if a valid serial digital input signal has been presented to the
device. If no valid serial data stream has been detected, the serial data into the device is
considered invalid, and the LOCKED signal is LOW.
Once a valid input signal has been detected, the device attempts to detect the presence
of either TRS words or DVB-ASI sync words.
By default, the device powers up in Auto mode (the AUTO_MAN bit in the host interface
is set HIGH). In this mode, the device operating frequency toggles between 3G, HD, and
SD rates as it attempts to lock to the incoming data rate. As it searches through rates,
PCLK output cycles through 148.5MHz, 74.25MHz, 27MHz, and 13.5MHz. The PCLK
output pin can be set to be high-impedance when not locked through GSPI.
When the device is operating in Manual mode (AUTO_MAN bit in the host interface
register is LOW), the operating frequency needs to be set through the RATE_SEL_TOP
bits in the host interface. RATE_SEL_TOP[0] = SD/HD and RATE_SEL_TOP[1] = 3G/HD.
Note: The SD/HD bit takes precedence over the 3G/HD bit, so if the SD/HD bit is HIGH,
the 3G/HD bit is ignored.
1
0
CARRIER DETECT (SD)
2
4
3
5
6
7
Reserved
Reserved
CARRIER DETECT
CARRIER DETECT (HD)
CARRIER DETECT (3G)
Reserved
Reserved
INT_CD_MODE_SEL
1
0
2
4
3
5
6
7
AFE_RD_CD_MUX_OUT
EQ_LOS
Reserved
Rate Change Detected
Reserved
Reserved
CARRIER DETECT and Rate Detect (for any rates
selected with DATA_RATE_DETECTION)
CARRIER DETECT and Rate Detect (for any rates
selected with DATA_RATE_DETECTION with an eight
40MHz pulse low when rate changes)
INT_SOURCE_SEL
EQ_STAT



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com