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MMA8652FC 数据表(PDF) 22 Page - NXP Semiconductors |
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MMA8652FC 数据表(HTML) 22 Page - NXP Semiconductors |
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22 / 65 page  MMA8652FC Sensors 22 Freescale Semiconductor, Inc. NOTE Auto-increment addresses that are not a simple increment are highlighted in bold. The auto-increment addressing is only enabled when device registers are read using I2C burst read mode. The internally stored auto-increment address is cleared whenever an I2C STOP condition is detected. TRANSIENT_CFG(1)(4) R/W 0x1D 0x1E 00000000 0x00 Transient functional block configuration TRANSIENT_SRC(1)(2) R 0x1E 0x1F 00000000 0x00 Transient event status register TRANSIENT_THS(1)(3) R/W 0x1F 0x20 00000000 0x00 Transient event threshold TRANSIENT_COUNT(1)(3) R/W 0x20 0x21 00000000 0x00 Transient debounce counter PULSE_CFG(1)(4) R/W 0x21 0x22 00000000 0x00 Pulse enable configuration PULSE_SRC(1)(2) R 0x22 0x23 00000000 0x00 Pulse detection source PULSE_THSX(1)(3) R/W 0x23 0x24 00000000 0x00 X pulse threshold PULSE_THSY(1)(3) R/W 0x24 0x25 00000000 0x00 Y pulse threshold PULSE_THSZ(1)(3) R/W 0x25 0x26 00000000 0x00 Z pulse threshold PULSE_TMLT(1)(4) R/W 0x26 0x27 00000000 0x00 Time limit for pulse PULSE_LTCY(1)(4) R/W 0x27 0x28 00000000 0x00 Latency time for 2nd pulse PULSE_WIND(1)(4) R/W 0x28 0x29 00000000 0x00 Window time for 2nd pulse ASLP_COUNT(1)(4) R/W 0x29 0x2A 00000000 0x00 Counter setting for Auto-SLEEP CTRL_REG1(1)(4) R/W 0x2A 0x2B 00000000 0x00 Data rates and modes setting CTRL_REG2(1)(4) R/W 0x2B 0x2C 00000000 0x00 Sleep Enable, OS modes, RST, ST CTRL_REG3(1)(4) R/W 0x2C 0x2D 00000000 0x00 Wake from Sleep, IPOL, PP_OD CTRL_REG4(1)(4) R/W 0x2D 0x2E 00000000 0x00 Interrupt enable register CTRL_REG5(1)(4) R/W 0x2E 0x2F 00000000 0x00 Interrupt pin (INT1/INT2) map OFF_X(1)(4) R/W 0x2F 0x30 00000000 0x00 X-axis offset adjust OFF_Y(1)(4) R/W 0x30 0x31 00000000 0x00 Y-axis offset adjust OFF_Z(1)(4) R/W 0x31 0x0D 00000000 0x00 Z-axis offset adjust 1. Register contents are preserved when a transition from ACTIVE to STANDBY mode occurs. 2. Register contents are reset when a transition from STANDBY to ACTIVE mode occurs. 3. Register contents can be modified at any time in either STANDBY or ACTIVE mode. A write to this register will cause a reset of the corresponding internal system debounce counter. 4. Register contents can only be modified while the device is in STANDBY mode; the only exceptions to this are the CTRL_REG1[ACTIVE] and CTRL_REG2[RST] bits. Table 12. MMA8652FC register address map (Continued) Name Type Register Address Auto-Increment Address Default Hex Value Comment FMODE = 0 F_READ = 0 FMODE > 0 F_READ = 0 FMODE = 0 F_READ = 1 FMODE > 0 F_READ = 1 |
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