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MMA8652FC 数据表(PDF) 37 Page - NXP Semiconductors

部件名 MMA8652FC
功能描述  MMA8652FC, 3-Axis, 12-bit, Digital Accelerometer
PDF  65 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MMA8652FC 数据表(HTML) 37 Page - NXP Semiconductors

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MMA8652FC
Sensors
Freescale Semiconductor, Inc.
37
6.8
Freefall/Motion configuration and status registers
The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15:
FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits (ZEFE, YEFE, XEFE) to zero.
Depending on the register bits ELE (0x15: FF_MTG_CFG, bit 7) and OAE (0x15: FF_MTG_CFG, bit 6), each of the freefall and
motion detection block can operate in four different modes.
6.8.1
Motion and freefall modes
6.8.1.1
Mode 1: Freefall detection with ELE = 0, OAE = 0
In this mode, the EA bit (0x16: FF_MTG_CFG, bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE,
YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM
= 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement
mode. If DBCNTM = 1, then the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before
the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit.
The event flags (0x16) ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any
debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.
6.8.1.2
Mode 2: Freefall detection with ELE = 1, OAE = 0
In this mode, the EA event bit indicates a freefall event after the debounce counter. Once the debounce counter reaches the time
value for the set threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the
FF_MT_SRC register is read, the EA bit and the debounce counter are cleared, and a new event can only be generated after the
delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall
detection. While EA = 0, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g
event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.
The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE,
YHP, XHE, and XHP will start changing only after the FF_MT_SRC register has been read.
6.8.1.3
Mode 3: Motion detection with ELE = 0, OAE = 1
In this mode, the EA bit indicates a motion event after the debounce counter time is reached. The ZEFE, YEFE, and XEFE control
bits determine which axes are taken into consideration for motion detection. Once the EA bit is set and if DBCNTM = 0, the EA
bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, then the EA bit is cleared as soon as the
motion high g condition disappears.
The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any
debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear
any flags, nor is the debounce counter reset.
6.8.1.4
Mode 4: Motion detection with ELE = 1, OAE = 1
In this mode, the EA bit indicates a motion event after debouncing. The ZEFE, YEFE, and XEFE control bits determine which
axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and
the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared
and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT.
While the bit EA is zero, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g
event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set,
these bits (ZHE, ZHP, YHE, YHP, XHE, XHP) keep their current value until the FF_MT_SRC register is read.



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