MMA8652FC datasheet(30/65 Pages) NXP

30 / 65 page

MMA8652FC

Sensors

Freescale Semiconductor, Inc.

6.5.3

0x0D: WHO_AM_I Device ID register

The device identification register identifies the part. The default value is 0x4A (for MMA8652FC).

This value is programmed by Freescale before the part leaves the factory. For custom alternate values, contact Freescale.

Table 26. INT_SOURCE register

Bit(s)

Field

Description

SRC_ASLP

Auto-SLEEP/WAKE interrupt status bit

• WAKE-to-SLEEP transition occurs when no interrupt occurs for a time period that exceeds the user-

specified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting.

• SLEEP-to-WAKE transition occurs when the user-specified interrupt event has woken the system; thus

causing the system to transition to a user-specified high ODR setting.

• Reading the SYSMOD register clears the SRC_ASLP bit.

1 An interrupt event that can cause a WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition has

occurred.

0 No WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition interrupt event has occurred. (default)

SRC_FIFO

FIFO interrupt status bit

• FIFO interrupt event generators: FIFO Overflow, or (Watermark: F_CNT = F_WMRK) and the interrupt has

been enabled.

• SRC_FIFO bit is cleared by reading the F_STATUS register.

1 A FIFO interrupt event (such as an overflow event or watermark) has occurred.

0 No FIFO interrupt event has occurred. (default)

SRC_TRANS

Transient interrupt status bit

• SRC_TRANS bit is asserted whenever the EA bit (TRANS_SRC register) is asserted and the interrupt has

been enabled.

• SRC_TRANS bit is cleared by reading the TRANS_SRC register.

1An acceleration transient value greater than user-specified threshold has occurred.

0 No transient event has occurred. (default)

SRC_LNDPRT

Landscape/Portrait Orientation interrupt status bit

• SRC_LNDPRT bit is asserted whenever the NEWLP bit (PL_STATUS register) is asserted and the interrupt

has been enabled.

• SRC_LNDPRT bit is cleared by reading the PL_STATUS register.

1 An interrupt was generated due to a change in the device orientation status.

0 No change in orientation status was detected. (default)

SRC_PULSE

Pulse interrupt status bit

• SRC_PULSE bit is asserted whenever the EA bit (PULSE_SRC register) is asserted and the interrupt has

been enabled.

• SRC_PULSE bit is cleared by reading the PULSE_SRC register.

1 An interrupt was generated due to single and/or double pulse event.

0 No pulse event was detected. (default)

SRC_FF_MT

Freefall/Motion interrupt status bit

• SRC_FF_MT bit is asserted whenever the EA bit (FF_MT_SRC register) is asserted and the FF_MT

interrupt has been enabled.

• SRC_FF_MT bit is cleared by reading the FF_MT_SRC register.

1 The Freefall/Motion function interrupt is active.

0 No Freefall or Motion event was detected. (default)

—

Could be 1 or 0.

SRC_DRDY

Data Ready Interrupt bit status bit

• SRC_DRDY bit is asserted when the ZYXOW and/or ZYXDR bit is set and the interrupt has been enabled.

• SRC_DRDY bit is cleared by reading the X, Y, and Z data.

1 The X, Y, Z data ready interrupt is active (indicating the presence of new data and/or data overrun).

0 The X, Y, Z interrupt is not active. (default)

Table 27. 0x0D: WHO_AM_I Device ID register (Read-Only)

Back to Register Address Map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

100

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