MMA8652FC datasheet(56/65 Pages) NXP

56 / 65 page

MMA8652FC

Sensors

Freescale Semiconductor, Inc.

6.12.4

0x2D: CTRL_REG4 Interrupt Enable register (Read/Write)

CTRL_REG4 register enables the following interrupts: Auto-WAKE/SLEEP, Orientation Detection, Freefall/Motion, and Data

Ready.

6.12.5

0x2E CTRL_REG5 Interrupt Configuration register (Read/Write)

CTRL_REG5 register maps the desired interrupts to INT2 or INT1 pins.

The system’s interrupt controller, shown in Figure 9, uses the corresponding bit field in the CTRL_REG5 register to determine the

routing table for the INT1 and INT2 interrupt pins.

•

If the bit value is 0, then the functional block’s interrupt is routed to INT2.

•

If the bit value is 1, then the functional block’s interrupt is routed to INT1.

One or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the

INT_SOURCE (0x0C) register, to determine the appropriate sources of the interrupt.

PP_OD

Push-Pull/Open-Drain selection on interrupt pad

Configures the interrupt pins to Push-Pull or to Open-Drain mode.

The Open-Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.

0 Push-Pull (default)

1 Open Drain

Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)

Back to Register Address Map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_EN_ASLP

INT_EN_FIFO

INT_EN_TRANS

INT_EN_LNDPRT

INT_EN_PULSE

INT_EN_FF_MT

INT_EN_DRDY

Table 105. CTRL_REG4 register

Bit(s)

Field

Description

INT_EN_ASLP

Auto-SLEEP/WAKE Interrupt Enable

0 interrupt is disabled (default)

1 interrupt is enabled

Note: The corresponding functional block interrupt

enable bit enables the functional block to route

its event detection flags to the system’s interrupt

controller. The interrupt controller routes the

enabled functional block interrupt to the INT1 or

INT2 pin.

INT_EN_FIFO

FIFO Interrupt Enable

INT_EN_TRANS

Transient Interrupt Enable

INT_EN_LNDPRT

Orientation (Landscape/Portrait) Interrupt Enable

INT_EN_PULSE

Pulse Detection Interrupt Enable

INT_EN_FF_MT

Freefall/Motion Interrupt Enable

INT_EN_DRDY

Data Ready Interrupt Enable

Table 106. 0x2E: CTRL_REG5 Interrupt Configuration register

Back to Register Address Map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_CFG_ASLP

INT_CFG_FIFO

INT_CFG_TRANS

INT_CFG_LNDPRT

INT_CFG_PULSE

INT_CFG_FF_MT

INT_CFG_DRDY

Table 107. 0x2E CTRL_REG5 register

Bit(s)

Field

Description

INT_CFG_ASLP

Auto-SLEEP/WAKE INT1/INT2 Configuration

0 Interrupt is routed to INT2 pin (default)

1 Interrupt is routed to INT1 pin

INT_CFG_FIFO

FIFO INT1/INT2 Configuration

INT_CFG_TRANS

Transient INT1/INT2 Configuration

INT_CFG_LNDPRT

Orientation INT1/INT2 Configuration

INT_CFG_PULSE

Pulse INT1/INT2 Configuration

INT_CFG_FF_MT

Freefall/motion INT1/INT2 Configuration

INT_CFG_DRDY

Data Ready INT1/INT2 Configuration

Table 103. CTRL_REG3 register (Continued)

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