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ADAR2004ACCZ-R7 数据表(PDF) 25 Page - Analog Devices |
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ADAR2004ACCZ-R7 数据表(HTML) 25 Page - Analog Devices |
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25 / 37 page  Data Sheet ADAR2004 Rev. 0 | Page 25 of 37 REGISTER SUMMARY Table 10. ADAR2004 Register Summary Address Name Bits Bit Name Description Reset Access 0x000 INTERFACE_CONFIG_A 7 SOFTRESET Soft Reset 0x0 R/W 6 LSB_FIRST LSB First 0x0 R/W 5 ADDR_ASCN Address Ascension 0x0 R/W 4 SDOACTIVE SDO Active 0x1 R/W 3 SDOACTIVE_ SDO Active 0x1 R/W 2 ADDR_ASCN_ Address Ascension 0x0 R/W 1 LSB_FIRST_ LSB First 0x0 R/W 0 SOFTRESET_ Soft Reset 0x0 R/W 0x001 INTERFACE_CONFIG_B 7 SINGLE_INSTRUCTION Single Instruction 0x0 R/W 6 CS_STALL CS Stall 0x0 R/W 5 MASTER_SLAVE_RB Master Slave Readback 0x0 R/W 4 SLOW_INTERFACE_CTRL Slow Interface Control 0x0 R/W 3 RESERVED Reserved 0x0 R [2:1] SOFT_RESET Soft Reset 0x0 R/W 0 RESERVED Reserved 0x0 R 0x002 DEV_CONFIG [7:4] DEV_STATUS Device Status 0x1 R/W [3:2] CUST_OPERATING_MODE Custom Operating Modes 0x0 R/W [1:0] NORM_OPERATING_MODE Normal Operating Modes 0x0 R/W 0x003 CHIP_TYPE [7:0] CHIP_TYPE Chip Type 0x0 R 0x004 PRODUCT_ID_H [7:0] PRODUCT_ID[15:8] Product ID High 0x0 R 0x005 PRODUCT_ID_L [7:0] PRODUCT_ID[7:0] Product ID Low 0x0 R 0x00A SCRATCH_PAD [7:0] SCRATCHPAD Scratch Pad 0x0 R/W 0x00B SPI_REV [7:0] SPI_REV SPI Revision 0x0 R 0x00C VENDOR_ID_H [7:0] VENDOR_ID[15:8] Vendor ID High 0x0 R 0x00D VENDOR_ID_L [7:0] VENDOR_ID[7:0] Vendor ID Low 0x0 R 0x00F TRANSFER_REG [7:1] RESERVED Reserved 0x0 R 0 MASTER_SLAVE_XFER Master Slave Transfer 0x0 R/W 0x010 PWRON [7:1] RESERVED Reserved 0x0 R 0 PWRON Chip Power-Up 0x1 R/W 0x011 BIAS_CURRENT_MULT1 [7:4] MULT_MID_BIAS Mid Band 4× Bias Current Setting 0x5 R/W [3:0] MULT_LOW_BIAS Low Band 4× Bias Current Setting 0x5 R/W 0x012 BIAS_CURRENT_MULT2 [7:4] RESERVED Reserved 0x0 R/W [3:0] MULT_HIGH_BIAS High Band 4× Bias Current Setting 0x7 R/W 0x013 BIAS_CURRENT_LOAMP [7:4] LO_AMP2_BIAS LO Amp Output Stage Bias Current Setting 0x7 R/W [3:0] LO_AMP1_BIAS LO Amp Input Stage Bias Current Setting 0x8 R/W 0x014 BIAS_CURRENT_SPLT [7:4] SPLT2_BIAS Second Active Splitter Stages Bias Current Setting 0x7 R/W [3:0] SPLT1_BIAS First Active Splitter Stage Bias Current Setting 0xA R/W 0x015 BIAS_CURRENT_LNAMIX [7:4] MIX_BIAS Mixer Bias Current Setting 0x2 R/W [3:0] LNA_BIAS LNA Bias Current Setting 0xA R/W 0x016 BIAS_CURRENT_IFAMP [7:4] IFAMP_BIAS IF Output Amp Bias Current Setting 0xC R/W [3:0] RESERVED Reserved 0x0 R/W 0x017 IFAMP_CM [7:4] RESERVED Reserved 0x0 R [3:0] IFAMP_CM IF Output Amp Common-Mode Voltage Setting 0x4 R/W 0x018 RX_SEQUENCER_SETUP 7 RX_SEQ_EN Enables Receiver Sequencer 0x0 R/W 6 RX_SLP_CTRL Sets Receiver Sleep Mode Control 0x0 R/W 5 RX_SLP_HOLD Holds the Receiver Sequencer State When Multiplier Is in Sleep Mode 0x0 R/W 4 RX_CTL_LATCH_BYP Bypasses the Control Latch for Receiver Controls 0x1 R/W [3:0] RX_STATES Sets Number of Receiver Sequencer States 0x0 R/W |
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