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ADAR2004ACCZ-R7 数据表(PDF) 27 Page - Analog Devices |
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ADAR2004ACCZ-R7 数据表(HTML) 27 Page - Analog Devices |
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27 / 37 page  Data Sheet ADAR2004 Rev. 0 | Page 27 of 37 Address Name Bits Bit Name Description Reset Access 0x02C RX_GAIN12_SPI 7 RESERVED Reserved 0x0 R [6:4] CH1_GAIN_SPI SPI Mode Channel 1 Gain Setting 0x0 R/W 3 RESERVED Reserved 0x0 R [2:0] CH2_GAIN_SPI SPI Mode Channel 2 Gain Setting 0x0 R/W 0x02D RX_GAIN34_SPI 7 RESERVED Reserved 0x0 R [6:4] CH3_GAIN_SPI SPI Mode Channel 3 Gain Setting 0x0 R/W 3 RESERVED Reserved 0x0 R [2:0] CH4_GAIN_SPI SPI Mode Channel 4 Gain Setting 0x0 R/W 0x02E SPLT_EN_SPI [7:3] RESERVED Reserved 0x0 R 2 SPLT1_EN_SPI SPI Mode Active Splitter 1 Enable 0x0 R/W 1 SPLT12_EN_SPI SPI Mode Channel 1 to Channel 2 Active Splitter Enable 0x0 R/W 0 SPLT34_EN_SPI SPI Mode Channel 3 to Channel 4 Active Splitter Enable 0x0 R/W 0x02F MULT_SPI 7 BPF_SPI SPI Mode BPF Select 0x0 R/W 6 LOAMP_EN_SPI SPI Mode LO Amplifier Enable 0x0 R/W 5 MULT_LOW_RDY_SPI SPI Mode Low Band Ready Enable 0x0 R/W 4 MULT_LOW_ACT_SPI SPI Mode Low Band Active Enable 0x0 R/W 3 MULT_MID_RDY_SPI SPI Mode Mid Band Ready Enable 0x0 R/W 2 MULT_MID_ACT_SPI SPI Mode Mid Band Active Enable 0x0 R/W 1 MULT_HIGH_RDY_SPI SPI Mode High Band Ready Enable 0x0 R/W 0 MULT_HIGH_ACT_SPI SPI Mode High Band Active Enable 0x0 R/W 0x030 ADC_CTRL 7 ADC_CLKFREQ_SEL ADC Clock Frequency Selection 0x0 R/W 6 ADC_EN Turns on Comparator and Resets State Machine 0x0 R/W 5 CLK_EN Turns on Clock Oscillator 0x0 R/W 4 ST_CONV Pulse Triggers Conversion Cycle 0x0 R/W [3:1] RESERVED Reserved 0x0 R/W 0 ADC_EOC ADC End of Conversion Signal 0x0 R 0x031 ADC_OUTPUT [7:0] ADC ADC Output Word 0x0 R 0x032 RX_STATUS [7:4] RX_CURR_STATE Read Back Current Receiver Sequencer Count 0x0 R [3:0] RX_CURR_MODE Read Back Current Receiver Mode 0x0 R 0x033 MULT_STATUS [7:4] MULT_CURR_STATE Read Back Current Multiplier/Filter Sequencer Count 0x0 R [3:0] MULT_CURR_MODE Read Back Current Mode 0x0 R 0x034 REV_ID [7:0] REV_ID Chip Revision ID 0x0 R 0x040 RX_EN_MODE_0 7 RESERVED Reserved 0x0 R 6 SPLT1_EN_MD0 Receiver Mode 0 Active Splitter 1 Enable 0x0 R/W 5 SPLT12_EN_MD0 Receiver Mode 0 Channel 1 to Channel 2 Active Splitter Enable 0x0 R/W 4 SPLT34_EN_MD0 Receiver Mode 0 Channel 3 to Channel 4 Active Splitter Enable 0x0 R/W 3 CH1_EN_MD0 Receiver Mode 0 Channel 1 Enable 0x0 R/W 2 CH2_EN_MD0 Receiver Mode 0 Channel 2 Enable 0x0 R/W 1 CH3_EN_MD0 Receiver Mode 0 Channel 3 Enable 0x0 R/W 0 CH4_EN_MD0 Receiver Mode 0 Channel 4 Enable 0x0 R/W 0x041 RX_GAIN12_MODE_0 7 RESERVED Reserved 0x0 R [6:4] CH1_GAIN_MD0 Receiver Mode 0 Channel 1 Gain 0x0 R/W 3 RESERVED Reserved 0x0 R [2:0] CH2_GAIN_MD0 Receiver Mode 0 Channel 2 Gain 0x0 R/W 0x042 RX_GAIN34_MODE_0 7 RESERVED Reserved 0x0 R [6:4] CH3_GAIN_MD0 Receiver Mode 0 Channel 3 Gain 0x0 R/W 3 RESERVED Reserved 0x0 R [2:0] CH4_GAIN_MD0 Receiver Mode 0 Channel 4 Gain 0x0 R/W |
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