Data Sheet

ADAR2004

Rev. 0 | Page 21 of 37

RECEIVER

RESET

MULTIPLIER

RESET

MULT_STATE_0

RX_STATE_0

SLEEP

MULT: ALL SLEEP

BPF:

N/A

Rx:

ALL CHANNELS

RECEIVER

ADVANCE

MULTIPLIER

ADVANCE

RECEIVER

ADVANCE

MULTIPLIER

ADVANCE

RECEIVER

ADVANCE

MULTIPLIER

ADVANCE

MULTIPLIER

ADVANCE

MULTIPLIER

ADVANCE

MULT_STATE_1

RX_STATE_1

CHANNEL 1

READY

MULT: MID READY

BPF:

N/A

Rx:

ALL CHANNELS

MULT_STATE_2

RX_STATE_2

CHANNEL 1

20GHz TO 25GHz

MULT: MID ACTIVE

BPF:

HIGH

Rx:

ALL CHANNELS

MULT_STATE_3

RX_STATE_2

CHANNEL 1

25GHz TO 30GHz

MULT: HIGH ACTIVE

BPF:

LOW

Rx:

ALL CHANNELS

MULT_STATE_4

RX_STATE_2

CHANNEL 1

30GHz TO 40GHz

MULT: HIGH ACTIVE

BPF:

HIGH

Rx:

ALL CHANNELS

Figure 43. Multiplier State Machine Operating Example for a Frequency Sweep of All Receiver Channels Simultaneously From 20 GHz to 40 GHz (N/A Means Not Applicable)

SEQUENCER SLEEP HOLD

By default, when one of the sequencers is forced asleep using one

of the sleep control bits (MULT_SLP_CTRL or RX_SLP_CTRL),

the counter for the sequencer being controlled can still be

advanced. Because of this behavior, it is possible for a state

machine to be put to sleep in one condition and brought out of

sleep in another, depending on whether the sequencer advance

or reset signals were exercised while the sequencer was sleeping.

If this behavior is undesired, the sleep hold bits

(MULT_SLP_HOLD and RX_SLP_HOLD) can be asserted to

force the associated state machine counter to ignore any inputs

on the sequencer advance line. The counter also ignores advance

signals coming from the SPI.

Note that the counter always responds to a reset signal, even

when the sleep hold bit is high.

When sleep hold is used, take care when bringing the state

machines out of sleep mode to ensure that the desired modes

are reached. If the advance pins for both sequencers are pulsed

too closely together under this condition, it is possible for the

sequencer being controlled to not move into the expected state.

To prevent this issue, stagger the advance pulses so that the

rising edges are separated by a minimum of 3 ns with the pulse

of the controlled sequencer coming second. See Figure 44 for an

example of how to pulse the sequencers under this condition.

≥3ns

MADV

RxADV

RX_SLP_HOLD REGISTER 0x018, BIT 5 = 1

RX_SLP_CTRL REGISTER 0x018, BIT 6 = 1

MULT_SLP_HOLD REGISTER 0x019, BIT 5 = 0

MULT_SLP_CTRL REGISTER 0x019, BIT 6 = 0

Figure 44. Example of How to Pulse the Sequencer Advance Pins to Ensure

Advancement With Receiver State Machine Sleep Hold Enabled

SEQUENCER CONTROL LATCH BYPASS

Typically, when a sequencer control line is pulsed, the upcoming

state is loaded on the rising edge of the control pulse and

latched to the various signal blocks on the falling edge of the

same pulse. The latching helps to line up all the internal control

signals so that the changes take place simultaneously.

It is possible to bypass the latching of the internal control signals by

setting the bypass bits (RX_CTL_LATCH_BYP and

MULT_CTL_LATCH_BYP) in the sequencer setup registers

(Register 0x018, Bit 4 and Register 0x019, Bit 4).

Bypassing the latch results in the new state taking effect as soon

as possible after the rising edge. Because the internal control

signals are not aligned, it is possible that the overall switching

time between states increases when compared to using the latch.

Also, glitches are more likely to occur in the internal control

signals, resulting in undesired transients in the RF blocks.

Note that this latch is the last check before any new data is sent

to the various individual blocks. Therefore, when using the

ADAR2004 in manual or SPI mode (sequencers disabled), the

latching must be bypassed. If the latching is not bypassed, the

blocks do not receive the new instructions unless the external

sequencer pins are pulsed. However, this issue is uncommon

because the sequencers are disabled in this mode of operation.