ADAR2004ACCZ-R7 datasheet(16/37 Pages) AD

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ADAR2004

Data Sheet

Rev. 0 | Page 16 of 37

THEORY OF OPERATION

OVERVIEW

The main elements of the ADAR2004 are a quad LNA, a mixer,

an IF variable gain amplifier (VGA), a 4× LO frequency multiplier

with integrated switchable harmonic filter, and a 1:4 signal splitter.

The four differential RF inputs are intended to be connected

directly to a differential antenna structure, such as a dipole. Apply

a single-tone LO input signal in the 2.4 GHz to 10.1 GHz

frequency range with a power level of approximately −20 dBm

to the LOIN port. This signal is frequency multiplied by 4 and

filtered before driving the LO inputs of the four mixers.

The operation of these subcircuits can be controlled from the

SPI port as well as two programmable state machines, one

focused on LO multiplier/filter control and the other focused

on quad receiver control.

The ADAR2004 also includes an Analog Devices, Inc., SPI port

that is used for device configuration and readback. Although

the state machines provide fast switching between states, all

functions can also be controlled directly through the SPI port.

LO INPUT BUFFER, 4× MULTIPLIER, AND BAND-

PASS FILTER

The LO input buffer provides approximately 17 dB of gain and

provides an optimal drive signal to the 4× multiplier circuits for

LO input power levels down to −25 dBm. The bias levels of the

input and output stages of the input buffer are independently

adjustable through the SPI via Register 0x013. See the Bias Points

and Voltages section for more information.

The broadband frequency multiplier consists of three parallel

subcircuits. Each subcircuit (low band, mid band, high band) is

optimized to multiply and filter a segment of the total frequency

range (2.4 GHz to 10.1 GHz input, 9.6 GHz to 40.4 GHz output).

Recommended ranges and register settings for each band are

shown in Table 7. SP3T switches at the input and output of the

multiplier block are used to select the desired subcircuit.

Each subcircuit consists of a 4× multiplier and an adjustable

band-pass filter (BPF). The bias levels of the 4× multipliers are

adjustable through the SPI via Register 0x011 and Register 0x012.

See the Bias Points and Voltages section for more information.

When the LO input frequency is in the low end of the subcircuit

band, the BPF corner frequency must be set to its low state. Set

the associated bit high to set the BPF corner frequency to its

low state. See Table 7.

To complete a full 9.6 GHz to 40.4 GHz frequency sweep,

adjust the multiplier/filter block settings six times to ensure

optimum harmonic rejection and output power. These six

settings are shown in Table 7.

In addition to having sleep and active modes, the 4× multipliers

can be set to ready mode. Ready mode is a hybrid state between

sleep and active mode. Current consumption in ready mode is

higher than sleep mode but lower than active mode. The switching

time between ready mode and active mode is significantly faster

than from sleep mode to active mode.

1:4 SIGNAL SPLITTER NETWORK

The output of the multiplier/filter block is then applied to a 1:4

active power splitting network that is composed of two stages.

The first stage is a 1:2 active splitter, which then feeds the second

stage, two 1:2 active splitters. Each output path from the second

stage drives a single downconverting mixer, which results in a

single input signal being split into four independently controlled

channels. The bias levels of each splitter stage are adjustable

through the SPI via Register 0x014. See the Bias Points and

Voltages section for more information.

Table 7. Multiplier/Filter Settings for Optimal LO Harmonic Rejection

LO Input Frequency

(GHz)

Internal LO Frequency

(GHz)

Multiplier Band

BPF

MULT_x1 Register Value

2.40 to 3.00

9.6 to 12

Low band active (mid and high bands ready)

Low

0xFA

3.00 to 4.00

12 to 16

Low band active (mid and high bands ready)

High

0x7A

4.00 to 5.00

16 to 20

Mid band active (mid and high bands ready)

Low

0xEE

5.00 to 6.25

20 to 25

Mid band active (low and high bands ready)

High

0x6E

6.25 to 8.00

25 to 32

High band active (low and mid bands ready)

Low

0xEB

8.00 to 10.10

32 to 40.4

High band active (low and mid bands ready)

High

0x6B

MULT_x refers to the MULT_EN_MODE_x and MULT_SPI registers.

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