ADAR2004ACCZ-R7 datasheet(19/37 Pages) AD

19 / 37 page

Data Sheet

ADAR2004

Rev. 0 | Page 19 of 37

•

Bit 4: MULT_CTL_LATCH_BYP. This bit bypasses the

latch on MADV and MRST. If the latch is enabled, the

next state is loaded up on the rising edge of a MRST or

MADV pulse. The state is then latched to the device on the

falling edge of the same pulse. If the latch is bypassed,

everything is applied as soon as possible after the rising

edge of the pulse, with no latching.

•

Bit 5: MULT_SLP_HOLD. This bit prevents the

multiplier/filter block from advancing when forced into a

sleep state by the receiver block. This bit is used in

conjunction with RX_SLP_CTRL (Register 0x018, Bit 6).

See the Sequencer Sleep Hold section for more

information.

•

Bit 6: MULT_SLP_CTRL. This bit forces the multiplier/filter

block to sleep whenever the receiver block is sleeping. See

the Sequencer Sleep Control section for more information.

•

Bit 7: MULT_SEQ_EN. This bit enables the multiplier/filter

block. This bit must be set high for the block to operate

with the external pins.

For the receiver sequencer, the control register is Register 0x018

and contains the following bits:

•

Bit 0 to Bit 3: RX_STATES. These bits set the number of

states in the loop (see Figure 42).

•

Bit 4: RX_CTL_LATCH_BYP. This bit bypasses the latch

on RxADV and RxRST. If the latch is enabled, the next state is

loaded up on the rising edge of an RxRST or RxADV pulse.

The state is then latched to the device on the falling edge of

the same pulse. If the latch is bypassed, everything is applied

as soon as possible after the rising edge of the pulse, with

no latching.

•

Bit 5: RX_SLP_HOLD. This bit prevents the receiver block

from advancing when forced into a sleep state by the

multiplier/filter block. This bit is used in conjunction with

MULT_SLP_CTRL (Register 0x019, Bit 6). See the

Sequencer Sleep Hold section for more information.

•

Bit 6: RX_SLP_CTRL. This bit forces the receiver block to

sleep whenever the multiplier/filter block is sleeping. See the

Sequencer Sleep Control section for more information.

•

Bit 7: RX_SEQ_EN. This bit enables the receiver block.

This bit must be set high for the block to operate with the

external pins.

MULTIPLIER/FILTER STATE MACHINE

A programmable state machine provides a convenient and fast

control mechanism for the multiplier/filter block and avoids the

need for SPI writes each time the block must be reconfigured.

To enable the state machine, set the MULT_SEQ_EN bit

(Register 0x019, Bit 7) high.

Although only six multiplier/filter modes are required for a

complete 9.6 GHz to 40.4 GHz sweep, as described in Table 7, a

maximum state machine depth of 16 is provided for optimum

flexibility.

Eight default modes can be assigned to any of the 16 states.

These eight modes consist of a sleep mode, a ready mode, and

the six modes required to complete a 9.6 GHz to 40.4 GHz sweep,

as described in Table 7. It is possible to overwrite any of the

multiplier/filter modes with a custom set of operating conditions

by changing the bits in Register 0x070 to Register 0x07F.

After the modes are defined, set the order in which the sequencer

moves through the desired modes by filling the state bits in

interest. Any state can point to any mode, except State 0, which

always points to Mode 0. Note that the sequencer moves

through the states in order, up to the state machine depth.

Finally, the user must define how many states are used by setting

the state machine depth (MULT_STATES, Register 0x019,

Bits[3:0]). MULT_STATES is 0 indexed. Therefore, setting the

depth to 0 leaves MULT_STATE_1 (Register 0x022, Bits[7:4])

as the only state in the loop.

After the multiplier/filter state machine is programmed and

enabled, operation is controlled by the MRST and MADV pins.

Alternatively, operation can be controlled through the SPI using

the MULT_RST_SPI and MULT_ADV_SPI bits (Register 0x02A,

Bit 3 and Bit 2, respectively). Note that using the SPI is slower

than pulsing the sequencer pins directly.

MRST moves the pointer on the multiplier/filter state machine

to State 0 regardless of the current position of the pointer and

can be asserted at any time. State 0 always refers to Mode 0 and

cannot be set to another mode. However, Mode 0 can be

overwritten with any multiplier/filter configuration. Mode 0 is

defined in Register 0x070.

MADV pulses advance the multiplier/filter state machine pointer

one state at a time until the defined sequencer depth is cycled

through. At that point, an additional MADV pulse moves the

pointer back to State 1, which is normally set to a ready mode

(however, State 1 can be set to any mode). State 1 applies the mode

defined in the MULT_STATE_1 bits (Register 0x022, Bits[7:4]).

RECEIVER STATE MACHINE

Like the multiplier/filter state machine, the receiver state

machine can be used to quickly cycle through receiver states

without using the comparatively slower SPI.

To enable the state machine, set the RX_SEQ_EN bit

(Register 0x018, Bit 7) high.

The receiver state machine controls the status of the four receive

channels (each with an LNA, mixer, and IF VGA) and the status of

the 1:4 splitter network by defining the desired modes of operation

in Register 0x040 to Register 0x06F. Each mode outlines a custom

set of operating conditions.

Although only one active state is required to enable all receive

channels, a state machine depth of 16 is provided for optimum

flexibility of the receiver sequencer and to lower the total number

of control lines required to operate multiple ADAR2004 chips in

parallel. It is possible to control up to 16 ADAR2004 ICs using the

ADAR2004ACCZ-R7 数据表(PDF) 19 Page - Analog Devices

ADAR2004ACCZ-R7 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载