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STM32L552CET6PTR 数据表(PDF) 19 Page - STMicroelectronics |
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STM32L552CET6PTR 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 340 page  DS12737 Rev 6 19/340 STM32L552xx Description 78 Figure 1. STM32L552xx block diagram 1. AF: alternate function on I/O pins. USB FS CH1 CH2 DAC1 Flash up to 512KB Flexible static memory controller (FSMC): SRAM, PSRAM, NOR Flash,FRAM, NAND Flash 114 AF PA[15:0] TIM1 / PWM 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF USART1 RX, TX, CK,CTS, RTS as AF SPI1 MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF OUT1 WWDG RTC_TS OSC32_IN OSC32_OUT VDDA, VSSA VDD, VSS, NRST smcard irDA 16b D[7:0], D[3:1]dir CMD, CMDdir,CK, CKin D0dir, D2dir VBAT = 1.55 to 3.6 V SCL, SDA, SMBA as AF JTAG & SW Arm Cortex-M33 110 MHz TrustZone FPU NVIC ETM MPU TRACECLK TRACED[3:0] CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT as AF RNG DP DM @ VDDA BOR Supply supervision PVD, PVM Int reset XTAL 32 kHz MAN A G T RTC Standby interface IWDG @VBAT @ VDD @VDD AWU Reset & clock control VDD = 1.71 to 3.6 V VSS Voltage Regulator LDO and SMPS 3.3 to 1.2 V VDD Power management @ VDD RTC_TAMP[8:1] Backup register TIM15 2 channels, 1 compl. channel, BKIN as AF TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 USART2 USART3 I2C1/SMBUS EXT. IT WKUP SDMMC1 GPIO PORT H GPIO PORT F GPIO PORT G GPIO PORT D GPIO PORT E GPIO PORT B GPIO PORT C GPIO PORT A DMA1 DMA2 SRAM 192 KB SRAM 64 KB NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO C-BUS S-BUS PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[1:0] TIM8 / PWM 16b 16b TIM16 16b TIM17 16b 3 compl. Channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF 1 channel, 1 compl. channel, BKIN as AF 1 channel, 1 compl. channel, BKIN as AF OUT2 16b 16b SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS as AF RX, TX, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF RX, TX, CK, CTS, RTS as AF smcard irDA smcard irDA 32b 16b 16b 32b 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF AHB/APB1 OSC_IN OSC_OUT XTAL OSC 4- 16MHz 16xIN VREF+ US AR T 2 M B p s Temperature sensor SAI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI2 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF DFSDM SDCKIN[7:0], SDDATIN[7:0], SDCKOUT,SDTRIG as AF Touch sensing controller 8 groups of sensing channels as AF OUT, INN, INP LPUART1 LPTIM1 LPTIM2 RX, TX, CTS, RTS as AF IN1, IN2, OUT, ETR as AF IN1, OUT, ETR as AF RC HSI RC LSI PLL 1&2&3 MSI Octo SPI1 memory interface IO[7:0], CLK, NCLK, NCS. DQS @ VDDUSB COMP1 INP, INN, OUT COMP2 INP, INN, OUT @ VDDA RTC_OUT VDDIO, VDDUSB CRC OUT, INN, INP I2C2/SMBUS I2C3/SMBUS OpAmp1 SPI3 SPI2 UART5 UART4 AHB2 110 MHz OpAmp2 @VDDA VREF Buffer @ VDDA @ VDD TX, RX as AF FDCAN1 SCL, SDA, SMBA as AF I2C4/SMBUS ITF ADC1 @ VDDA ADC2 LPTIM3 IN1, OUT, ETR as AF UCPD1 DP DM @ VDDUSB CRS DMAMUX1 SYSCFG AHB/APB2 MSv49361V6 HASH GTZC 32-bits APB bus VBAT power domain VDDA power domain VDDUSB power domain 32-bits AHB bus VDD power domain VDDIO2 power domain |
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