STM32L552CET6PTR datasheet(21/340 Pages) STMICROELECTRONICS

21 / 340 page

DS12737 Rev 6

21/340

STM32L552xx

Functional overview

ICACHE offers the following features:

•

Multi-bus interface:

–

slave port receiving the memory requests from the Cortex®-M33 C-AHB code

execution port

–

master1 port performing refill requests to internal memories (FLASH and SRAMs)

–

master2 port performing refill requests to external memories (external

FLASH/RAMs through Octo-SPI/FMC interfaces)

–

a second slave port dedicated to ICACHE registers access.

•

Close to zero wait states instructions/data access performance:

–

0 wait-state on cache hit

–

hit-under-miss capability, allowing to serve new processor requests while a line

refill (due to a previous cache miss) is still ongoing

–

critical-word-first refill policy, minimizing processor stalls on cache miss

–

hit ratio improved by 2-ways set-associative architecture and pLRU-t replacement

policy (pseudo-least-recently-used, based on binary tree), algorithm with best

complexity/performance balance

–

dual master ports allowing to decouple internal and external memory traffics, on

Fast and Slow buses, respectively; also minimizing impact on interrupt latency

–

optimal cache line refill thanks to AHB burst transactions (of the cache line size).

–

performance monitoring by means of a hit counter and a miss counter.

•

Extension of cacheable region beyond Code memory space, by means of address

remapping logic that allows to define up to 4 cacheable external regions

•

Power consumption reduced intrinsically (most accesses to cache memory rather to

bigger main memories); even improved by configuring ICACHE as direct mapped

(rather than the default 2-ways set-associative mode)

•

TrustZone® security support

•

Maintenance operation for software management of cache coherency

•

Error management: detection of unexpected cacheable write access, with optional

interrupt raising.

3.3

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory

and to prevent one task to accidentally corrupt the memory or the resources used by any

other active task. This memory area is organized into up to 8 regions for secure and 8

regions for non secure state.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

STM32L552CET6PTR 数据表(PDF) 21 Page - STMicroelectronics

STM32L552CET6PTR 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载