STM32L552CET6PTR datasheet(20/340 Pages) STMICROELECTRONICS

20 / 340 page

Functional overview

STM32L552xx

20/340

DS12737 Rev 6

Functional overview

3.1

Arm® Cortex®-M33 core with TrustZone® and FPU

The Cortex®-M33 with TrustZone and FPU is a highly energy efficient processor designed

for microcontrollers and deeply embedded applications, especially those requiring efficient

security.

The Cortex®-M33 processor delivers a high computational performance with low-power

consumption and an advanced response to interrupts. it features:

•

Arm® TrustZone® technology, using the Armv8-M main extension supporting secure

and non-secure states

•

Memory protection units (MPUs), 8 regions for secure and 8 regions for non secure

•

Configurable secure attribute unit (SAU) supporting up to 8 memory regions

•

Floating-point arithmetic functionality with support for single precision arithmetic

The processor supports a set of DSP instructions that allows an efficient signal processing

and a complex algorithm execution.

The Cortex®-M33 processor supports the following bus interfaces:

•

System AHB bus:

The System AHB (S-AHB) bus interface is used for any instruction fetch and data

access to the memory-mapped SRAM, peripheral, external RAM and external device,

or Vendor_SYS regions of the Armv8-M memory map.

•

Code AHB bus

The Code AHB (C-AHB) bus interface is used for any instruction fetch and data access

to the code region of the Armv8-M memory map.

Figure 1 shows the general block diagram of the STM32L552xx family devices.

3.2

Art Accelerator – instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex®-M33

processor to improve performance when fetching instruction (or data) from both internal and

external memories.

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