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STM32L552CET6PTR 数据表(PDF) 41 Page - STMicroelectronics |
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STM32L552CET6PTR 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 340 page ![]() Stop 1 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...4)(7) LPTIMx (x=1,2) *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...4)(7) LPTIMx (x=1,2) USB_FS(8) Stop 2 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIMx (x= 1,3) *** All other peripherals are frozen Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIMx (x= 1,3) Table 10. STM32L552xx modes overview (continued) Mode Regulator and SMPS mode(1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source |
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