ADBMS1818ASWZ-R7 datasheet(32/89 Pages) AD

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Data Sheet

ADBMS1818

THEORY OF OPERATION

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Rev. 0 | 32 of 89

Overlap Cell Measurement (ADOL Command)

The ADOL command first simultaneously measures Cell 7 with

ADC1 and ADC2. Then, the ADOL command simultaneously meas-

ures Cell 13 with both ADC2 and ADC3. The host can compare

the results against each other to look for inconsistencies that may

indicate a fault. The result of the Cell 7 measurement from ADC2

is placed in Cell Voltage Register Group C where the Cell 7 result

normally resides. The result from ADC1 is placed in Cell Voltage

result of the Cell 13 measurement from ADC3 is placed in Cell

Voltage Register Group E where the Cell 13 result normally resides.

The result from ADC2 is placed in Cell Voltage Register Group E

where the Cell 14 result normally resides. Figure 61 shows the

timing of the ADOL command. See the Commands section for the

ADOL command format.

Figure 61. Timing for ADOL Command

Table 27 shows the conversion time for the ADOL command. t2C

indicates the total conversion time for this command.

Table 27. Conversion Times for ADOL Command

Mode

Conversion Times (μs)

t1M

t2M

t2C

27 kHz 0

106

384

14 kHz 0

164

442

7 kHz

146

281

791

Table 27. Conversion Times for ADOL Command

Mode

Conversion Times (μs)

t1M

t2M

t2C

3 kHz

262

513

1024

2 kHz

495

979

1490

1 kHz

960

1910

2420

422 Hz 0

1891

3772

4282

26 Hz

29,818

59,626

67,119

Digital Filter Check

The Δ-Σ ADC is composed of a 1-bit pulse density modulator

followed by a digital filter. A pulse density modulated bit stream has

a higher percentage of 1s for higher analog input voltages. The

digital filter converts this high frequency 1-bit stream into a single

16-bit word.

This is why a Δ-Σ ADC is often referred to as an oversampling

converter.

The self test commands verify the operation of the digital filters

and memory. Figure 62 shows the operation of the ADC during self

test. The output of the 1-bit pulse density modulator is replaced by

a 1-bit test signal. The test signal passes through the digital filter

and is converted to a 16-bit value. The 1-bit test signal undergoes

the same digital conversion as the regular 1-bit signal from the

modulator, so the conversion time for any self test command is

exactly the same as the corresponding regular ADC conversion

command. The 16-bit ADC value is stored in the same register

groups as the corresponding regular ADC conversion command.

The test signals are designed to place alternating one-zero patterns

in the registers. Table 28 provides a list of the self test commands.

If the digital filters and memory are working properly, then the

registers contain the values shown in Table 28. For more details

see the Commands section.

Figure 62. Operation of ADBMS1818 ADC Self Test

Table 28. Self Test Command Summary

Command

Self Test Option

Output Pattern in Different ADC Modes

Results Register Groups

27 kHz

14 kHz

7 kHz, 3 kHz, 2 kHz, 1 kHz, 422 Hz, 26 Hz

CVST

ST, Bits[1:0] = 01

0x9565

0x9553

0x9555

C1V to C18V (CVA, CVB, CVC, CVD, CVE, CVF)

ST, Bits[1:0] = 10

0x6A9A

0x6AAC

0x6AAA

AXST

ST, Bits[1:0] = 01

0x9565

0x9553

0x9555

G1V to GV9, REF (AUXA, AUXB, AUXC, AUXD)

ST, Bits[1:0] = 10

0x6A9A

0x6AAC

0x6AAA

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