ADBMS1818ASWZ-R7 datasheet(39/89 Pages) AD

39 / 89 page

Data Sheet

ADBMS1818

THEORY OF OPERATION

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Rev. 0 | 39 of 89

COMM Commands

Three commands help accomplish I2C or SPI communication to the

slave device: WRCOMM, STCOMM, and RDCOMM.

WRCOMM Command: This command is used to write data to the

COMM register. This command writes 6 bytes of data to the COMM

PEC does not match, all data in the COMM register is cleared to

1s when CSB goes high. See the Bus Protocols section for more

details on a write command format.

STCOMM Command: This command initiates I2C/SPI communica-

tion on the GPIO ports. The COMM register contains 3 bytes of

data to be transmitted to the slave. During this command, the data

bytes stored in the COMM register are transmitted to the slave I2C

or SPI device and the data received from the I2C or SPI device is

stored in the COMM register. This command uses GPIO4 (SDA),

and GPIO5 (SCL) for I2C communication or GPIO3 (CSBM), GPIO4

(SDIOM), and GPIO5 (SCKM) for SPI communication.

The STCOMM command is followed by 24 clock cycles for each

byte of data transmitted to the slave device while holding CSB low.

For example, to transmit three bytes of data to the slave, send

the STCOMM command and its PEC followed by 72 clock cycles.

Pull CSB high at the end of the 72 clock cycles of the STCOMM

command.

During I2C or SPI communication, the data received from the slave

device is updated in the COMM register.

RDCOMM Command: The data received from the slave device

can be read back from the COMM register using the RDCOMM

command. The command reads back six bytes of data followed by

the PEC. See the Bus Protocols section for more details on a read

command format.

Table 37 describes the possible read back codes for ICOMn,

Bits[3:0] and FCOMn, Bits[3:0] when using the device as an I2C

master. Dn, Bits[7:0] contain the data byte transmitted by the I2C

slave.

Table 37. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C

Master

Control

Bits

Code

Description

ICOMn,

Bits[3:0]

0110

Master generated a start signal

0001

Master generated a stop signal

0000

Blank, SDA was held low between bytes

0111

Blank, SDA was held high between bytes

FCOMn,

Bits[3:0]

0000

Master generated an ACK signal

0111

Slave generated an ACK signal

1111

Slave generated a NACK signal

0001

Slave generated an ACK signal, master generated a

stop signal

Table 37. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C

Master

Control

Bits

Code

Description

1001

Slave generated a NACK signal, master generated a

stop signal

In case of the SPI master, the read back codes for ICOMn, Bits[3:0]

and FCOMn, Bits[3:0] are always 0111 and 1111, respectively. Dn,

Bits[7:0] contain the data byte transmitted by the SPI slave.

Figure 64 shows the operation of ADBMS1818 as an I2C or SPI

master using the GPIOs.

Figure 64. ADBMS1818 I2C or SPI Master Using GPIOs

Any number of bytes can be transmitted to the slave in groups

of 3 bytes using these commands. The GPIO ports do not reset

between different STCOMM commands. However, if the wait time

between the commands is greater than 2 sec, the watchdog times

out and resets the ports to their default values.

To transmit several bytes of data using an I2C master, a start

signal is only required at the beginning of the entire data stream.

A stop signal is only required at the end of the data stream. All

intermediate data groups can use a blank code before the data byte

and an ACK/NACK signal as appropriate after the data byte. SDA

and SCL do not reset between different STCOMM commands.

To transmit several bytes of data using an SPI master, a CSBM

low signal is sent at the beginning of the 1st data byte. CSBM can

be held low or taken high for intermediate data groups using the

appropriate code on FCOMn, Bits[3:0]. A CSBM high signal is sent

at the end of the last byte of data. CSBM, SDIOM, and SCKM do

not reset between different STCOMM commands.

Figure 65 shows the 24 clock cycles following the STCOMM com-

mand for an I2C master in different cases. Note that if ICOMn,

Bits[3:0] specified a stop condition, after the stop signal is sent, the

SDA and SCL lines are held high and all data in the rest of the word

is ignored. If ICOMn, Bits[3:0] are a no transmit, both SDA and SCL

lines are released, and the rest of the data in the word is ignored.

This is used when a particular device in the stack does not have to

communicate to a slave.

Figure 66 shows the 24 clock cycles following the STCOMM com-

mand for an SPI master. Similar to the I2C master, if ICOMn,

Bits[3:0] specified a CSBM HIGH or a no transmit condition, the

CSBM, SCKM, and SDIOM lines of the SPI master are released

and the rest of the data in the word is ignored.

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