ADBMS1818ASWZ-R7 datasheet(68/89 Pages) AD

68 / 89 page

Data Sheet

ADBMS1818

APPLICATIONS INFORMATION

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Rev. 0 | 68 of 89

PROVIDING DC POWER

Simple Linear Regulator

The primary supply pin for the ADBMS1818 is the 5 V (±0.5 V)

VREG input pin. To generate the required 5 V supply for VREG,

the DRIVE pin can be used to form a discrete regulator with the

addition of a few external components, as shown in Figure 93. The

DRIVE pin provides a 5.7 V output, capable of sourcing 1 mA.

When buffered with an NPN transistor, the DRIVE pin provides a

stable 5 V over temperature. The NPN transistor must be chosen

to have a sufficient Beta over temperature (> 40) to supply the

necessary supply current. The peak VREG current requirement of

the ADBMS1818 approaches 35 mA when simultaneously commu-

nicating over isoSPI and making ADC conversions. If the VREG pin

is required to support any additional load, a transistor with an even

higher Beta may be required.

Figure 93. Simple VREG Power Source Using NPN Pass Transistor

The NPN collector can be powered from any voltage source that

is a minimum 6 V above V–. This includes the cells that are being

monitored, or an unregulated power supply. A 100 Ω, 100 nF

RC decoupling network is recommended for the collector power

connection to protect the NPN from transients. The emitter of the

NPN must be bypassed with a 1 µF capacitor. Larger capacitance

must be avoided because this increases the wake-up time of the

ADBMS1818. Some attention must be given to the thermal charac-

teristic of the NPN, as there can be significant heating with a high

collector voltage.

Improved Regulator Power Efficiency

For improved efficiency when powering the ADBMS1818 from the

cell stack, VREG can be powered from a dc-to-dc converter, rather

than the NPN pass transistor. An ideal circuit is based on the

LT8631 step-down regulator, as shown in Figure 94. A 100 Ω

resistor is recommended between the battery stack and the LT8631

input, which prevents in-rush current when connecting to the stack

and reduces conducted electromagnetic interference (EMI). The

EN/UV pin must be connected to the DRIVE pin, which puts the

LT8631 into a low power state when the ADBMS1818 is in the sleep

state.

Figure 94. VREG Powered From Cell Stack with High Efficiency Regulator

INTERNAL PROTECTION AND FILTERING

Internal Protection Features

The ADBMS1818 incorporates various ESD safeguards to ensure

robust performance. An equivalent circuit showing the specific

protection structures is shown in Figure 95. Zener- like suppressors

are shown with their nominal clamp voltage, and the unmarked

diodes exhibit standard PN junction behavior.

Filtering of Cell and GPIO Inputs

The ADBMS1818 uses a Δ-Σ ADC, which includes a Δ-Σ modulator

followed by a sinc3 finite impulse response (FIR) digital filter,

which greatly relaxes input filtering requirements. Furthermore, the

programmable oversampling ratio allows the user to determine

the best trade-off between measurement speed and filter cutoff fre-

quency. Even with this high order low-pass filter, fast transient noise

can still induce some residual noise in measurements, especially

in the faster conversion modes. This noise can be minimized by

adding an RC, low-pass decoupling to each ADC input, which also

helps reject potentially damaging high energy transients. Adding

more than about 100 Ω to the ADC inputs begins to introduce a

systematic error in the measurement, which can be improved by

raising the filter capacitance or mathematically compensating in

software with a calibration procedure. For situations that demand

the highest level of battery voltage ripple rejection, grounded ca-

pacitor filtering is recommended. This configuration has a series

resistance and capacitors that decouple high frequency noise to

V–. In systems where noise is less periodic or higher oversampling

rates are in use, a differential capacitor filter structure is adequate.

In this configuration there are series resistors to each input, but

the capacitors connect between the adjacent C pins. However,

the differential capacitor sections interact. As a result, the filter

response is less consistent and results in less attenuation than

predicted by the RC, by approximately a decade. Note that the

capacitors only see one cell of applied voltage (thus smaller and

lower cost) and tend to distribute transient energy uniformly across

the IC (reducing stress events on the internal protection structure).

Figure 96 shows the two methods schematically. ADC accuracy

varies with R and C as shown in the typical performance curves,

but the error is minimized if R = 100 Ω and C = 10 nF. The GPIO

pins always use a grounded capacitor configuration because the

measurements are all with respect to V–.

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