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ADBMS1818ASWZ-R7 数据表(PDF) 36 Page - Analog Devices

部件名 ADBMS1818ASWZ-R7
功能描述  18-Cell Battery Monitor with Daisy Chain Interface
PDF  89 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADBMS1818ASWZ-R7 数据表(HTML) 36 Page - Analog Devices

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Data Sheet
ADBMS1818
THEORY OF OPERATION
analog.com
Rev. 0 | 36 of 89
Table 31. Discharge Timer Settings
Watchdog Timer
Discharge Timer
DTEN = 0, DCTO = XXXX Resets CFGAR0-5,
CFGBR0-1 and SCTRL
when it fires
Disabled
DTEN = 1, DCTO = 0000
Resets CFGAR0-5,
CFGBR0-1 and SCTRL
when it fires
Disabled
DTEN = 1, DCTO != 0000 Resets CFGAR0-3 and
GPIO Bits in CFGBR0
when it fires
Resets CFGAR4-5,
SCTRL, and remainder of
CFGBR0-1 when it fires
Table 31 summarizes the status of the configuration register groups
after a watchdog timer or discharge timer event. The status of
the discharge timer can be determined by reading Configuration
Register Group A using the RDCFGA command. The DCTO value
indicates the time left before the discharge timer expires, as shown
in Table 32.
Table 32. Status of the Discharge Timer
DCTO (Read Value)
Discharge Timer Left (Minutes)
0
Disabled (or) timer has timed out
1
0 < timer ≤ 0.5
2
0.5 < timer ≤ 1
3
1 < timer ≤ 2
4
2 < timer ≤ 3
5
3 < timer ≤ 4
6
4 < timer ≤ 5
7
5 < timer ≤ 10
8
10 < timer ≤ 15
9
15 < timer ≤ 20
A
20 < timer ≤ 30
B
30 < timer ≤ 40
C
40 < timer ≤ 60
D
60 < timer ≤ 75
E
75 < timer ≤ 90
F
90 < timer ≤ 120
Unlike the watchdog timer, the discharge timer does not reset
when there is a valid command. The discharge timer can only be
reset after a valid WRCFGA (Write Configuration Register Group A)
command. There is a possibility that the discharge timer expires in
the middle of some commands.
If the discharge timer activates in the middle of a WRCFGA com-
mand, the configuration register groups and S Control Register
Group (including S control bits in PWM/S Control Register Group B)
reset as per Table 31. However, at the end of the valid WRCFGA
command, the new data is copied to Configuration Register Group
A. The new configuration data is not lost when the discharge timer
is activated.
If the discharge timer activates in the middle of a RDCFGA or
RDCFGB command, the configuration register groups reset as per
Table 31. As a result, the read back data from bytes CFGAR4
and CFGAR5 and CFGBR0 and CFGBR1 may be corrupted. If the
discharge timer activates in the middle of a RDSCTRL or RDPSB
command, the S Control Register Group (including S control bits in
PWM/S Control Register Group B) resets, as per Table 31. As a
result, the read back data may be corrupted.
S PIN PULSE-WIDTH MODULATION FOR CELL
BALANCING
For additional control of cell discharging, the host may configure
the S pins to operate using PWM. While the watchdog timer is
not expired, the DCC bits in the configuration register groups
control the S pins directly. After the watchdog timer expires, PWM
operation begins and continues for the remainder of the selected
discharge time or until a wake-up event occurs (and the watchdog
timer is reset). During PWM operation, the DCC bits must be set to
1 for the PWM feature to operate.
Once PWM operation begins, the configurations in the PWM regis-
ter can cause some or all S pins to be periodically deasserted to
achieve the desired duty cycle as shown in Table 33. Each PWM
signal operates on a 30 second period. For each cycle, the duty
cycle can be programmed from 0% to 100% in increments of 1/15 =
6.67% (2 seconds).
Each S pin PWM signal is sequenced at different intervals to ensure
that no two pins switch on or off at the same time. The switching
interval between channels is 62.5 ms, and 1.125 sec is required for
all 18 pins to switch (18 × 62.5 ms).
Table 33. S Pin Pulse-Width Modulation Settings
DCC Bit
(Configuration
Register
Groups)
PWMC
Setting
On Time
(sec)
Off Time
(sec)
Duty Cycle
(%)
0
4’bXXXX
0
Continuously
Off
0
1
4’b1111
Continuously
On
0
100.0
1
4’b1110
28
2
93.3
1
4’b1101
26
4
86.7
1
4’b1100
24
6
80.0
1
4’b1011
22
8
73.3
1
4’b1010
20
10
66.7
1
4’b1001
18
12
60.0
1
4’b1000
16
14
53.3
1
4’b0111
14
16
46.7
1
4’b0110
12
18
40.0
1
4’b0101
10
20
33.3
1
4’b0100
8
22
26.7
1
4’b0011
6
24
20.0
1
4’b0010
4
26
13.3
1
4’b0001
2
28
6.7
1
4’b0000
0
Continuously
Off
0



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