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ADRF6750ACPZ-R7 数据表(PDF) 30 Page - Analog Devices

部件名 ADRF6750ACPZ-R7
功能描述  950 MHz to 1575 MHz Quadrature Modulator with Integrated Fractional-N PLL and VCO
PDF  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6750ACPZ-R7 数据表(HTML) 30 Page - Analog Devices

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ADRF6750
Rev. A | Page 30 of
40
Table 19. Register CR24 (Address 0x18), Autocalibration
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Disable autocalibration
0 = enable autocalibration (default)
1 = disable autocalibration
Table 20. Register CR27 (Address 0x1B), LO Monitor Output
and External VCO Control
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
External VCO control
0 = internal VCO selected
1 = external VCO selected
2
Power up LO monitor output
0 = power down (default)
1 = power up
[1:0]
Monitor output power into 50 Ω
00 = −24 dBm (default)
01 = −18 dBm
10 = −12 dBm
11 = −6 dBm
Table 21. Register CR28 (Address 0x1C), Internal VCO
Power-Down
Bit
Description
7
Reserved
6
Reserved
5
Internal VCO power-down
0 = power up (default)
1 = power down
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Table 22. Register CR29 (Address 0x1D), Modulator
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Power up modulator
0 = power down (default)
1 = power up
Table 23. Register CR30 (Address 0x1E), Attenuator
Bit
Description
7
Reserved
6
Reserved
[5:0]
Attenuator A5 to Attenuator A0
000000 = 0 dB
000001 = 1 dB
000010 = 2 dB
…
011111 = 31 dB
110000 = 32 dB
110001 = 33 dB
…
111101 = 45 dB
111110 = 46 dB
111111 = 47 dB
Table 24. Register CR33 (Address 0x21), Revision Code1
Bit
Description
7
Revision code
6
Revision code
5
Revision code
4
Revision code
3
Revision code
2
Revision code
1
Revision code
0
Revision code
1 Read-only register.



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