ADRF6750ACPZ-R7 datasheet(19/40 Pages) AD

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ADRF6750

Rev. A | Page 19 of

CLR2

DOWN

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 55. PFD Simplified Schematic

Lock Detect (LDET)

LDET (Pin 44) signals when the PLL has achieved lock to an

error frequency of less than 100 Hz. On a write to Register CR0,

a new PLL acquisition cycle starts, and the LDET signal goes

low. When lock has been achieved, this signal returns high.

Voltage-Controlled Oscillator (VCO)

The VCO core in the ADRF6750 consists of two separate VCOs,

each with 16 overlapping bands. Figure 56 shows an acquisition

plot demonstrating both the VCO overlap at roughly 1260 MHz

and the multiple overlapping bands within each VCO. The

choice of two 16-band VCOs allows a wide frequency range to

be covered without a large VCO sensitivity (KVCO) and resultant

poor phase noise and spurious performance. Note that the VCO

range is larger than the 2× LO frequency range of the part to

ensure that the device has enough margin to cover the full

frequency range over all conditions.

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

2.5

800

900

1000

1100

1200

1300

1400

1500

1600

1700

LO FREQUENCY (MHz)

Figure 56. VTUNE vs. LO Frequency

The correct VCO and band are chosen automatically by the

VCO and band select circuitry when Register CR0 is updated.

This is referred to as autocalibration.

The autocalibration time is set to 50 μs. During this time, the

VCO VTUNE is disconnected from the output of the loop filter

and is connected to an internal reference voltage. A typical

frequency acquisition is shown in Figure 57.

100

10k

100k

10M

100M

20 40 60 80 100 120 140 160 180 200 220 240 260 280 300

TIME (µs)

AUTOCAL

TIME (µs)

ACQUISITION TO 100Hz

Figure 57. PLL Acquisition

After autocalibration, normal PLL action resumes and the

correct frequency is acquired to within a frequency error of

100 Hz in 170 μs typically.

For a maximum cumulative step of 100 kHz, autocalibration

can be turned off by Register CR24, Bit 0. This enables cumu-

lative PLL acquisitions of 100 kHz or less to occur without the

autocalibration procedure, which improves acquisition times

significantly (see Figure 58).

100

10k

100k

100

150

200

TIME (µs)

ACQUISITION TO 100Hz

Figure 58. PLL Acquisition Without Autocalibration for 100 kHz Step

The VCO displays a variation of KVCO as VTUNE varies within

the band and from band to band. Figure 59 shows how the

KVCO varies across the full LO frequency range. Also shown

is the average value for each of the frequency bands. Figure 59

is useful when calculating the loop filter bandwidth and

individual loop filter components.

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