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ADRF6750ACPZ-R7 数据表(PDF) 6 Page - Analog Devices

部件名 ADRF6750ACPZ-R7
功能描述  950 MHz to 1575 MHz Quadrature Modulator with Integrated Fractional-N PLL and VCO
PDF  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6750ACPZ-R7 数据表(HTML) 6 Page - Analog Devices

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ADRF6750
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SPI Interface Timing
Table 3.
Parameter1
Symbol
Limit
Unit
CLK Frequency
fCLK
20
MHz max
CLK Pulse Width High
t1
15
ns min
CLK Pulse Width Low
t2
15
ns min
Start Condition Hold Time
t3
5
ns min
Data Setup Time
t4
10
ns min
Data Hold Time
t5
5
ns min
Stop Condition Setup Time
t6
5
ns min
SDO Access Time
t7
15
ns min
CS to SDO High Impedance
t8
25
ns max
1 See Figure 3.
t1
t3
CS
CLK
SDI
SDO
t6
t8
t7
t2
t5
t4
Figure 3. SPI Port Timing Diagram



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