ADRF6750ACPZ-R7 datasheet(4/40 Pages) AD

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ADRF6750

Rev. A | Page 4 of 4

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

GAIN CONTROL

Gain Range

Step Size

Relative Step Accuracy

Fixed frequency, adjacent steps

All attenuation steps

±0.3

Over full frequency range, adjacent steps

±1.5

Absolute Step Accuracy2

47 dB attenuation step

−2.0

Output Settling Time

Any step; output power settled to ±0.2 dB

μs

OUTPUT DISABLE

TXDIS pin

Off Isolation

RF OUT, attenuator setting = 0 dB to 47 dB, TXDIS high

−110

dBm

LO, Attenuator setting = 0 dB to 47 dB, TXDIS high

−90

dBm

2 x LO, Attenuator setting = 0 dB to 47 dB, TXDIS high

−50

dBm

Turn-On Settling Time

TXDIS high to low (90% of envelope)

180

Turn-Off Settling Time

TXDIS low to high (to −55 dBm)

270

MONITOR OUTPUT

LOMONP, LOMONN pins

Nominal Output Power

−24

dBm

BASEBAND INPUTS

IBBP, IBBN, QBBP, QBBN pins

I and Q Input Bias Level

500

1 dB Bandwidth

250

MHz

LOGIC INPUTS

Input High Voltage, VINH

CS, TXDIS pins

1.4

Input Low Voltage, VINL

CS, TXDIS pins

0.6

Input High Voltage, VINH

SDI/SDA, CLK/SCL pins

2.1

Input Low Voltage, VINL

SDI/SDA, CLK/SCL pins

1.1

Input Current, IINH/IINL

CS, TXDIS, SDI/SDA, CLK/SCL pins

±1

μA

Input Capacitance, CIN

CS, TXDIS, SDI/SDA, CLK/SCL pins

LOGIC OUTPUTS

Output High Voltage, VOH

SDO, LDET pins; IOH = 500 μA

2.8

Output Low Voltage, VOL

SDO, LDET pins; IOL = 500 μA

0.4

SDA (SDI/SDA); IOL = 3 mA

0.4

POWER SUPPLIES

VCC1, VCC2, VCC3, VCC4, VREG1, VREG2, VREG3, VREG4,

VREG5, VREG6, and REGOUT pins

REGOUT normally connected to VREG1, VREG2, VREG3,

VREG4, VREG5, and VREG6

Voltage Range

VCC1, VCC2, VCC3, and VCC4

4.75

5.25

REGOUT, VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6

3.3

Supply Current

VCC1, VCC2, VCC3, and VCC4 combined; REGOUT con-

nected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6

310

340

Operating Temperature

−40

+85

°C

1 LBW = 50 kHz at LO = 1200 MHz; ICP = 2.5 mA.

2 All other attenuation steps have an absolute error of <±2.0 dB.

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