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ADRF6750

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THEORY OF OPERATION

×2

DOUBLER

5-BIT

R-DIVIDER

FROM

REFIN

PFD

÷2

OVERVIEW

The ADRF6750 device can be divided into the following basic

building blocks:

Figure 53. Reference Input Path

The PFD frequency equation is

•

PLL synthesizer and VCO

fPFD = fREFIN × [(1 + D)/(R × (1 + T))]

(2)

•

Quadrature modulator

•

Attenuator

where:

fREFIN is the reference input frequency.

D is the doubler bit.

R is the programmed divide ratio of the binary 5-bit

programmable reference divider (1 to 32).

T is the divide-by-2 bit (0 or 1).

•

Voltage regulator

•

I2C/SPI interface

Each of these building blocks is described in detail in the

sections that follow.

PLL SYNTHESIZER AND VCO

RF Fractional-N Divider

Overview

The RF fractional-N divider allows a division ratio in the PLL

feedback path that can range from 23 to 4095. The relationship

between the fractional-N divider and the LO frequency is

described in the following section.

The phase-locked loop (PLL) consists of a fractional-N frequency

synthesizer with a 25-bit fixed modulus, allowing a frequency

resolution of less than 1 Hz over the entire frequency range. It

also has an integrated voltage-controlled oscillator (VCO) with

a fundamental output frequency ranging from 1900 MHz to

3150 MHz. This allows the PLL to generate a stable frequency at

2× LO, which is then divided down to provide a local oscillator

(LO) frequency ranging from 950 MHz to 1575 MHz to the

quadrature modulator.

INT and FRAC Relationship

The integer (INT) and fractional (FRAC) values make it

possible to generate output frequencies that are spaced by

fractions of the phase frequency detector (PFD) frequency.

See the Example—Changing the LO Frequency section for

more information.

Reference Input Section

The LO frequency equation is

The reference input stage is shown in Figure 52. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

open. This ensures that there is no loading of the REFIN pin at

power-down.

LO = fPFD × (INT + (FRAC/225))

(1)

where:

LO is the local oscillator frequency.

fPFD is the PFD frequency.

INT is the integer component of the required division factor

and is controlled by the CR6 and CR7 registers.

FRAC is the fractional component of the required division

factor and is controlled by the CR0 to CR3 registers.

BUFFER

R-DIVIDER

REFIN

100k

Ω

SW2

SW3

SW1

POWER-DOWN

CONTROL

N-COUNTER

INT

REG

PFD

RF N-DIVIDER

N = INT + FRAC/225

FROM VCO

OUTPUT

DIVIDERS

FRAC

VALUE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

Figure 52. Reference Input Stage

Reference Input Path

The on-chip reference frequency doubler allows the input

reference signal to be doubled. This is useful for increasing the

PFD comparison frequency. Making the PFD frequency higher

improves the noise performance of the system. Doubling the

PFD frequency usually improves the in-band phase noise

performance by 3 dBc/Hz.

Figure 54. RF Fractional-N Divider

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R-divider and the N-counter and

produces an output proportional to the phase and frequency differ-

ence between them (see Figure 55 for a simplified schematic).

The PFD includes a fixed delay element that sets the width of

the antibacklash pulse, ensuring that there is no dead zone in

the PFD transfer function.

The 5-bit R-divider allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 32 are allowed.

An additional divide-by-2 function in the reference input path

allows for a greater division range.

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