ADRF6750ACPZ-R7 datasheet(21/40 Pages) AD

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ADRF6750

Rev. A | Page 21 of

Optimization

The carrier feedthrough and the sideband suppression perfor-

mance of the ADRF6750 can be improved over the numbers

specified in Table 1 by using the following optimization

techniques.

Carrier Feedthrough Nulling

Carrier feedthrough results from dc offsets that occur between

the P and N inputs of each of the differential baseband inputs.

Normally these inputs are set to a dc bias of approximately 500 mV.

However, if a dc offset is introduced between the P and N inputs of

either or both I and Q inputs, the carrier feedthrough is affected

in either a positive or a negative fashion. Note that the dc bias

level remains at 500 mV (average P and N level). The I channel

offset is often held constant while the Q channel offset is varied

until a minimum carrier feedthrough level is obtained. Then,

while retaining the new Q channel offset, the I channel offset is

adjusted until a new minimum is reached. This is usually per-

formed at a single frequency and, thus, is not optimized over

the complete frequency range. Multiple optimizations at different

frequencies must be performed to ensure optimum carrier feed-

through across the full frequency range.

Sideband Suppression Nulling

Sideband suppression results from relative gain and relative

phase offsets between the I channel and Q channel and can

be optimized through adjustments to those two parameters.

Adjusting only one parameter improves the sideband suppression

only to a point. For optimum sideband suppression, an iterative

adjustment between phase and amplitude is required.

ATTENUATOR

The digital attenuator consists of six attenuation blocks: 1 dB,

2 dB, 4 dB, 8 dB, and two 16 dB blocks; each is separately

controlled. Each attenuation block consists of field effect

transistor (FET) switches and resistors that form either a pi-

shaped or a T-shaped attenuator. By controlling the states of the

FET switches through the control lines, each attenuation block

can be set to the pass state (0 dB) or the attenuation state (n dB).

The various combinations of the six blocks provide the

attenuation states from 0 dB to 47 dB in 1 dB increments.

VOLTAGE REGULATOR

The voltage regulator is powered from a 5 V supply that is

provided by VCC1 (Pin 11) and produces a 3.3 V nominal

regulated output voltage, REGOUT, on Pin 12. This pin must

be connected (external to the IC) to the VREG1 through VREG6

package pins.

The regulator output (REGOUT) should be decoupled by

a parallel combination of 10 pF and 220 μF capacitors. The

220 μF capacitor, which is recommended for best performance,

decouples broadband noise, leading to better phase noise. Each

VREGx pin should have the following decoupling capacitors:

100 nF multilayer ceramic with an additional 10 pF in parallel,

both placed as close as possible to the DUT power supply pins.

X7R or X5R capacitors are recommended. See the Evaluation

Board section for more information.

EXTERNAL VCO OPERATION

The ADRF6750 can be operated with an external VCO. This

can be useful if the user wants to improve the phase noise

performance or extend the frequency range. Note that the

external VCO needs to operate at a frequency of 2× LO.

To operate the ADRF6750 with an external VCO, follow

these steps:

Connect the charge pump output (Pin 9) to the loop filter

and onward to the external VCO input.

The KVCO of the external VCO needs to be taken into

account when calculating the loop bandwidth and loop

filter components. Note that a 50 kHz loop bandwidth is

recommended when using the internal VCO. This takes

into account the phase noise performance of the internal

VCO. It is possible for an external VCO to provide better

phase noise performance and a 50 kHz loop bandwidth

may not be optimal in that case. When selecting a loop

bandwidth, consider rms jitter, phase noise performance,

and acquisition time. ADISimPLL™ can be used to optim-

ize the loop bandwidth with a variety of external VCOs.

Connect the output of the external VCO to the TESTLO

and TESTLO input pins.

It is likely that a low-pass filter will be needed to filter the

output of the external VCO. This is very important if the

external VCO has poor second harmonic performance.

Second harmonic performance directly impacts sideband

suppression performance. For example, −30 dBc second

harmonic performance leads to −30 dBc sideband suppres-

sion. Both TESTLO and TESTLO need to be dc biased. A

dc bias of 1.7 V to 3.3 V is recommended. The REGOUT

output provides a 3.3 V output voltage.

Select external VCO operation by setting the following bits:

•

Set Register CR27[3] = 1. This bit multiplexes the

TESTLO and TESTLO through to the quadrature

modulator.

•

Set Register CR28[5] = 1. This bit powers down the

internal VCO and connects the external VCO to

the PLL.

Set the correct polarity for the PFD based on the slope of

the KVCO. The default is for positive polarity. This bit is

accessed by Register CR12[3].

When selecting an external VCO, at times it is difficult to select

one with an appropriate frequency range and KVCO. One solu-

tion may be the ADF4350, which can function as VCO only

with a range of 137.5 MHz to 4.4 GHz. Note that the ADF4350

requires an autocalibration time of 100 μs which directly

impacts acquisition time.

I2C INTERFACE

The ADRF6750 supports a 2-wire, I2C-compatible serial bus

that drives multiple peripherals. The serial data (SDA) and serial

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