ADRF6750ACPZ-R7 datasheet(22/40 Pages) AD

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ADRF6750

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clock (SCL) inputs carry information between any devices that

are connected to the bus. Each slave device is recognized by

a unique address. The ADRF6750 has two possible 7-bit slave

addresses for both read and write operations. The MSB of the

7-bit slave address is set to 1. Bit 5 of the slave address is set by

the CS pin (Pin 27). Bits[4:0] of the slave address are set to all

0s. The slave address consists of the seven MSBs of an 8-bit

word. The LSB of the word sets either a read or a write oper-

ation (see Figure 63). Logic 1 corresponds to a read operation,

whereas Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must

be followed. The master initiates a data transfer by establishing

a start condition, defined by a high-to-low transition on SDA

while SCL remains high. This indicates that an address/data

stream follows. All peripherals respond to the start condition

and shift the next eight bits (the 7-bit address and the R/W bit).

The bits are transferred from MSB to LSB. The peripheral that

recognizes the transmitted address responds by pulling the data

line low during the ninth clock pulse. This is known as an

acknowledge bit. All other devices then withdraw from the bus

and maintain an idle condition. During the idle condition, the

device monitors the SDA and SCL lines waiting for the start

condition and the correct transmitted address. The R/W bit

determines the direction of the data. Logic 0 on the LSB of the

first byte indicates that the master writes information to the

peripheral. Logic 1 on the LSB of the first byte indicates that the

master reads information from the peripheral.

The ADRF6750 acts as a standard slave device on the bus. The

data on the SDA pin (Pin 29) is eight bits long, supporting the

7-bit addresses plus the R/W bit. The ADRF6750 has 34 subad-

dresses to enable the user-accessible internal registers. Therefore,

it interprets the first byte as the device address and the second

byte as the starting subaddress. Autoincrement mode is supported,

which allows data to be read from or written to the starting sub-

address and each subsequent address without manually addressing

the subsequent subaddress. A data transfer is always terminated

by a stop condition. The user can also access any unique subaddress

Stop and start conditions can be detected at any stage of the data

transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. If an invalid subaddress is issued by the

user, the ADRF6750 does not issue an acknowledge and returns

to the idle condition. In a no acknowledge condition, the SDA

line is not pulled low on the ninth pulse. See Figure 64 and

Figure 65 for sample write and read data transfers, Figure 66 for

the timing protocol, and Figure 2 for a more detailed timing

diagram.

MSB = 1

SET BY

PIN 27

(CS)

0 = WR

1 = RD

SLAVE ADDRESS[6:0]

R/W

CTRL

Figure 63. Slave Address Configuration

SLAVE ADDR, LSB = 0 (WR)

A(S)

DATA

SUBADDR

A(S)

DATA

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

Figure 64. I2C Write Data Transfer

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(M) = NO ACKNOWLEDGE BY MASTER

SLAVE ADDR, LSB = 0 (WR)

SLAVE ADDR, LSB = 1 (RD)

A(S)

SUBADDR

A(S) DATA

A(M)

DATA

A(M)

Figure 65. I2C Read Data Transfer

START BIT

STOP BIT

ACK

SLAVE

ADDR[4:0]

SLAVE ADDRESS

SUBADDRESS

DATA

SUBADDR[6:1]

DATA[6:1]

SCL

SDA

Figure 66. I2C Data Transfer Timing

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