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ADRF6750ACPZ-R7 数据表(PDF) 5 Page - Analog Devices

部件名 ADRF6750ACPZ-R7
功能描述  950 MHz to 1575 MHz Quadrature Modulator with Integrated Fractional-N PLL and VCO
PDF  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6750ACPZ-R7 数据表(HTML) 5 Page - Analog Devices

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ADRF6750
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40
TIMING CHARACTERISTICS
I2C Interface Timing
Table 2.
Parameter1
Symbol
Limit
Unit
SCL Clock Frequency
fSCL
400
kHz max
SCL Pulse Width High
tHIGH
600
ns min
SCL Pulse Width Low
tLOW
1300
ns min
Start Condition Hold Time
tHD;STA
600
ns min
Start Condition Setup Time
tSU;STA
600
ns min
Data Setup Time
tSU;DAT
100
ns min
Data Hold Time
tHD;DAT
300
ns min
Stop Condition Setup Time
tSU;STO
600
ns min
Data Valid Time
tVD;DAT
900
ns max
Data Valid Acknowledge Time
tVD;ACK
900
ns max
Bus Free Time
tBUF
1300
ns min
1 See Figure 2.
SDA
tHD;STA
tSU;DAT
START
CONDITION
STOP
CONDITION
S
SS
P
SCL
1/
fSCL
tHIGH
tLOW
tHD;DAT
tVD;DAT AND
tVD;ACK (ACK SIGNAL ONLY)
tBUF
tSU;STO
tSU;STA
Figure 2. I2C Port Timing Diagram



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