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SPC58EEX 数据表(PDF) 70 Page - STMicroelectronics |
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SPC58EEX 数据表(HTML) 70 Page - STMicroelectronics |
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70 / 154 page ![]() Electrical characteristics SPC58EEx, SPC58NEx 70/154 DS11646 Rev 4 tSM2NM_TX CC T Transmitter startup time (sleep mode to normal mode)(7) Not applicable to the MSC/DSPI LVDS pad —0.4 0.6 µs tPD2NM_RX CC T Receiver startup time (power down to normal mode)(8) — — 20 40 ns tPD2SM_RX CC T Receiver startup time (power down to sleep mode)(9) Not applicable to the MSC/DSPI LVDS pad —20 50 ns ILVDS_BIAS CC D LVDS bias current consumption Tx or Rx enabled — — 0.95 mA TRANSMISSION LINE CHARACTERISTICS (PCB Track) Z0 SR D Transmission line characteristic impedance —47.5 50 52.5 Ω ZDIFF SR D Transmission line differential impedance — 95 100 105 Ω RECEIVER VICOM SR T Common mode voltage — 0.15 (10) —1.6(11) V | ΔVI| SR T Differential input voltage(12) —100 — — mV VHYS CC T Input hysteresis — 25 — — mV RIN CC D Terminating resistance VDD_HV_IO = 5.0 V ± 10% -40 °C<TJ<150 °C 80 — 150 Ω VDD_HV_IO = 3.3 V ± 10% -40 °C<TJ < 150 °C 80 — 175 VDD_HV_IO = 5.0 V ± 10% -40 °C<Tj<165 °C 80 — 170 VDD_HV_IO = 3.3 V ± 10% -40 °C<Tj<165 °C 80 — 180 CIN CC D Differential input capacitance(13) — — 3.5 6.0 pF ILVDS_RX CC C Receiver DC current consumption Enabled — — 1.6 mA IPIN_RX CC D Maximum consumption on receiver input pin ΔVI =400 mV, RIN =80 Ω —— 5 mA 1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions. 2. All LVDS pad electrical characteristics are valid from -40 °C to 150 °C. 3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding SIUL2 MSCR ODC field. Table 32. LVDS pad startup and receiver electrical characteristics(1),(2) (continued) Symbol C Parameter Conditions Value Unit Min Typ Max |
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