SPC58EEX datasheet(71/154 Pages) STMICROELECTRONICS

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DS11646 Rev 4

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SPC58EEx, SPC58NEx

Electrical characteristics

4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter

electrical characteristic tables.

5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being en-

abled.

6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock peri-

ods.

7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.

9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block re-

mains enabled in sleep mode.

10. Absolute min = 0.15 V – (285 mV/2) = 0 V

11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

12. Value valid for LFAST mode and SPI mode. In LFAST mode the LXRXOP_BR bit in the LFAST LVDS Control Register

(LCR) must be set to one to ensure proper LFAST receive timing.

13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. For bare

die devices, subtract the package value given in Figure 12.

Table 33. LFAST transmitter electrical characteristics(1),(2),(3)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

fDATA

SR D

Data rate

—

320

Mbps

VOS

CC P

Common mode voltage

—

1.08

—

1.32

ΔVOD|CC P

Differential output voltage swing

(terminated)(4),(5)

—

110

—

285

tTR

CC T

Rise time from -|

ΔVOD(min)| to

ΔVOD(min)|. Fall time from

ΔVOD(min)| to -|ΔVOD(min)|

—

0.26

—

1.25

SR D

External lumped differential load

capacitance(4)

VDD_HV_IO = 4.5 V

—

6.0

VDD_HV_IO = 3.0 V

—

4.0

ILVDS_TX CC C

Transmitter DC current consumption

Enabled

—

3.6

IPIN_TX

CC D

Transmitter DC current sourced through

output pin

—

1.1

2.85

1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101).

2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance

values shown in Figure 12.

3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 165 °C.

4. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in

Figure 12.

5. Valid for maximum external load CL.

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