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SPC58EEX 数据表(PDF) 73 Page - STMicroelectronics |
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SPC58EEX 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 154 page ![]() DS11646 Rev 4 73/154 SPC58EEx, SPC58NEx Electrical characteristics 74 Figure 12. LVDS pad external load diagram 3.14.3 LFAST PLL electrical characteristics The following table contains the electrical characteristics for the LFAST PLL. 3. All MSC and DSPI LVDS pad electrical characteristics are valid from -40 °C to 165 °C. 4. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in Figure 12. 5. Valid for maximum external load CL. 6. The transition time is measured from 10% to 90% of the voltage transition from -| ΔVOD|(min) to +|ΔVOD|(min). 1pF 1pF 2.5pF 2.5pF CL CL 100 Ω terminator Die Package PCB GPIO Driver LVDS Driver GPIO Driver Table 36. LFAST PLL electrical characteristics(1) Symbol C Parameter Conditions Value Unit Min Typ Max fRF_REF SR D PLL reference clock frequency (CLKIN) — 10(2) —30 MHz ERRREF CC D PLL reference clock frequency error — -1 — 1 % |
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